vendorcode/amd/pi/00670F00: remove unused headers
These header files are not used, so remove them. BUG=b:68812513 TEST=Build Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Martin Roth
parent
5bb0d75566
commit
42ac307330
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@ -1,51 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* AMD Pushhigh Interface
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*
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* Contains interface to Pushhigh entry
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Legacy
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* @e \$Revision$ @e \$Date$
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*
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
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* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef _DISPATCHER_H_
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#define _DISPATCHER_H_
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// AGESA function prototypes
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AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
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AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
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#endif // _DISPATCHER_H_
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@ -1,222 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* General Services
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*
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* Provides Services similar to the external General Services API, except
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* suited to use within AGESA components. Socket, Core and PCI identification.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Common
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* @e \$Revision$ @e \$Date$
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*
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef _GENERAL_SERVICES_H_
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#define _GENERAL_SERVICES_H_
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/*----------------------------------------------------------------------------------------
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* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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#define NUMBER_OF_EVENT_DATA_PARAMS 4
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/**
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* AMD Device id for MMIO check.
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*/
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#define AMD_DEV_VEN_ID 0x1022
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#define AMD_DEV_VEN_ID_ADDRESS 0
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S, S T R U C T U R E S, E N U M S
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*----------------------------------------------------------------------------------------
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*/
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/**
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* An AGESA Event Log entry.
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*/
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typedef struct {
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AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
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UINT32 EventInfo; ///< Uniquely identifies the event.
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UINT32 DataParam1; ///< Event specific additional data
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UINT32 DataParam2; ///< Event specific additional data
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UINT32 DataParam3; ///< Event specific additional data
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UINT32 DataParam4; ///< Event specific additional data
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} AGESA_EVENT;
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/*----------------------------------------------------------------------------------------
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* F U N C T I O N P R O T O T Y P E
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*----------------------------------------------------------------------------------------
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*/
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/**
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* Get a specified Core's APIC ID.
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*
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* @param[in] StdHeader Header for library and services.
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* @param[in] Socket The Core's Socket.
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* @param[in] Core The Core id.
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* @param[out] ApicAddress The Core's APIC ID.
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* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
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*
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* @retval TRUE The core is present, APIC Id valid
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* @retval FALSE The core is not present, APIC Id not valid.
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*/
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BOOLEAN
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GetApicId (
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IN AMD_CONFIG_PARAMS *StdHeader,
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IN UINT32 Socket,
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IN UINT32 Core,
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OUT UINT8 *ApicAddress,
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OUT AGESA_STATUS *AgesaStatus
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);
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/**
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* Get Processor Module's PCI Config Space address.
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*
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* @param[in] StdHeader Header for library and services.
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* @param[in] Socket The Core's Socket.
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* @param[in] Module The Module in that Processor
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* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
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* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
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*
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* @retval TRUE The core is present, PCI Address valid
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* @retval FALSE The core is not present, PCI Address not valid.
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*/
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BOOLEAN
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GetPciAddress (
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IN AMD_CONFIG_PARAMS *StdHeader,
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IN UINT32 Socket,
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IN UINT32 Module,
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OUT PCI_ADDR *PciAddress,
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OUT AGESA_STATUS *AgesaStatus
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);
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/**
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* "Who am I" for the current running core.
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*
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* @param[in] StdHeader Header for library and services.
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* @param[out] Socket The current Core's Socket
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* @param[out] Module The current Core's Processor Module
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* @param[out] Core The current Core's core id.
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* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
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*
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*/
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VOID
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IdentifyCore (
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IN AMD_CONFIG_PARAMS *StdHeader,
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OUT UINT32 *Socket,
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OUT UINT32 *Module,
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OUT UINT32 *Core,
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OUT AGESA_STATUS *AgesaStatus
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);
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/*---------------------------------------------------------------------------------------*/
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/**
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* Is this the BSP core?
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*
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* @param[in,out] StdHeader Header for library and services
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*
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* @retval TRUE Is BSP core
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* @retval FALSE Is not BSP Core
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*
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*/
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BOOLEAN
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IsBsp (
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IN OUT AMD_CONFIG_PARAMS *StdHeader
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);
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/**
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* This function logs AGESA events into the event log.
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*/
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VOID
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PutEventLog (
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IN AGESA_STATUS EventClass,
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IN UINT32 EventInfo,
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IN UINT32 DataParam1,
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IN UINT32 DataParam2,
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IN UINT32 DataParam3,
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IN UINT32 DataParam4,
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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/**
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* This function gets event logs from the circular buffer.
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*/
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AGESA_STATUS
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GetEventLog (
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OUT AGESA_EVENT *EventRecord,
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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/**
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* This function gets event logs from the circular buffer without flushing the entry.
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*/
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BOOLEAN
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PeekEventLog (
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OUT AGESA_EVENT *EventRecord,
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IN UINT16 Index,
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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/*---------------------------------------------------------------------------------------*/
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/**
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* This routine programs the registers necessary to get the PCI MMIO mechanism
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* up and functioning.
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*/
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VOID
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InitializePciMmio (
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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/*---------------------------------------------------------------------------------------*/
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/**
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*
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* Is it SecureS3
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*
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* @param[in] StdHeader Header for library and services
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*
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* @retval TRUE It's SecureS3
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* @retval FALSE It's NOT SecureS3
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*
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*/
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BOOLEAN
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IsSecureS3 (
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IN AMD_CONFIG_PARAMS *StdHeader
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);
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#endif // _GENERAL_SERVICES_H_
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@ -1,68 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* AGESA options structures
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*
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* Contains options control structures for the AGESA build options
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Core
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* @e \$Revision$ @e \$Date$
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
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* its contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef _OPTIONS_H_
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#define _OPTIONS_H_
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/**
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* Provide topology limits for loops and runtime, based on supported families.
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*/
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typedef struct {
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UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
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///< supported families and other build options.
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UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
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///< on supported families.
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} OPTIONS_CONFIG_TOPOLOGY;
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/**
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* Dispatch Table.
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*
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* The push high dispatcher uses this table to find what entries are currently in the build image.
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*/
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typedef struct {
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UINT32 FunctionId; ///< The function id specified.
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IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
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} DISPATCH_TABLE;
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#endif // _OPTIONS_H_
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@ -1,137 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* AMD CPU Execution Cache Allocation functions.
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*
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* Contains code for doing Execution Cache Allocation for ROM space
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: CPU
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* @e \$Revision$ @e \$Date$
|
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*
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*/
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/*****************************************************************************
|
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*
|
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
|
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
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#ifndef _CPU_CACHE_INIT_H_
|
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#define _CPU_CACHE_INIT_H_
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define BSP_STACK_SIZE_64K 65536
|
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#define BSP_STACK_SIZE_32K 32768
|
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|
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#define CORE0_STACK_SIZE 16384
|
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#define CORE1_STACK_SIZE 4096
|
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|
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#define AMD_MTRR_FIX4K_BASE 0x268
|
||||
#define AMD_MTRR_VARIABLE_BASE6 0x20C
|
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#define AMD_MTRR_VARIABLE_BASE7 0x20E
|
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|
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#define WP_IO 0x0505050505050505ull
|
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|
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#define AGESA_CACHE_SIZE_REDUCED 1
|
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#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
|
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#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
|
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#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
|
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#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
|
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#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
|
||||
#define AGESA_DEALLOCATE_CACHE_REGIONS 7
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
/// Cache-As-Ram Executable region allocation modes
|
||||
typedef enum {
|
||||
LimitedByL2Size, ///< Execution space must be allocated from L2
|
||||
InfiniteExe, ///< Family can support unlimited Execution space
|
||||
MaxCarExeMode ///< Used as limit or bounds check
|
||||
} CAR_EXE_MODE;
|
||||
|
||||
/// Cache Information
|
||||
typedef struct {
|
||||
IN UINT32 BspStackSize; ///< Stack size of BSP
|
||||
IN UINT32 Core0StackSize; ///< Stack size of primary cores
|
||||
IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
|
||||
IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
|
||||
IN UINT32 SharedMemSize; ///< Shared memory size
|
||||
IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
|
||||
IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
|
||||
IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
|
||||
IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
|
||||
} CACHE_INFO;
|
||||
|
||||
/// Merged memory region overlap type
|
||||
typedef enum {
|
||||
EmptySet, ///< One of the regions is zero length
|
||||
Disjoint, ///< The two regions do not touch
|
||||
Adjacent, ///< one region is next to the other, no gap
|
||||
CommonEnd, ///< regions overlap with a common end point
|
||||
Extending, ///< the 2nd region is extending the size of the 1st
|
||||
Contained, ///< the 2nd region is wholely contained inside the 1st
|
||||
CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
|
||||
Identity, ///< the two regions are the same
|
||||
CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
|
||||
NotCombinable ///< the combined regions do not follow the cache block rules
|
||||
} OVERLAP_TYPE;
|
||||
|
||||
/// Result of merging two memory regions for cache coverage
|
||||
typedef struct {
|
||||
IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
|
||||
IN OUT UINT32 MergedSize; ///< Size of the merged regions
|
||||
OUT UINT32 OverlapAmount; ///< the size of the overlapping section
|
||||
OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
|
||||
} MERGED_CACHE_REGION;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
AGESA_STATUS
|
||||
AllocateExecutionCache (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
|
||||
);
|
||||
|
||||
#endif // _CPU_CACHE_INIT_H_
|
||||
|
||||
|
|
@ -1,213 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD CPU Reset API, and related functions and structures.
|
||||
*
|
||||
* Contains code that initialized the CPU after early reset.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU
|
||||
* @e \$Revision$ @e \$Date$
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _CPU_EARLY_INIT_H_
|
||||
#define _CPU_EARLY_INIT_H_
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
//----------------------------------------------------------------------------
|
||||
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
|
||||
#define LOW_NODE_DEVICEID 24
|
||||
#define NB_CAPABILITIES 0xE8 //Function 3 Registers
|
||||
//----------------------------------------------------------------------------
|
||||
// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
/* All lengths are in bytes */
|
||||
#define MICROCODE_TRIADE_SIZE 28
|
||||
#define MICROCODE_HEADER_LENGTH 64
|
||||
|
||||
/**
|
||||
* @page ucodeflag Microcode Patches Signature Guide
|
||||
*
|
||||
* We mark patches in the ROM with a signature so that they can be easily found
|
||||
*
|
||||
* @anchor Microcode Patch Signature
|
||||
* @li @e Microcode Patch Signature @n
|
||||
* Microcode patches are marked by adding a signature before patches in the ROM image to
|
||||
* help identify where they are located.
|
||||
* There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
|
||||
* The other is '$UCODE4K', it indicates there's a following patch with 4K size.
|
||||
* If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
|
||||
*
|
||||
*
|
||||
*/
|
||||
/// Microcode patch flag for replacement
|
||||
typedef struct {
|
||||
IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
|
||||
} MICROCODE_PATCHES_FLAG;
|
||||
|
||||
#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
|
||||
#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
|
||||
#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
|
||||
|
||||
/* Offsets in UCODE PATCH Header */
|
||||
/* Note: Header is 64 bytes */
|
||||
#define DATE_CODE_OFFSET 0 // 4 bytes
|
||||
#define PATCH_ID 4 // 4 bytes
|
||||
#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
|
||||
#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
|
||||
#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
|
||||
#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
|
||||
#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
|
||||
#define PROCESSOR_REV_ID 24 // 2 bytes
|
||||
#define CHIPSET_1_REV_ID 26 // 1 byte
|
||||
#define CHIPSET_2_REV_ID 27 // 1 byte
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S, S T R U C T U R E S, E N U M S
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
//----------------------------------------------------------------------------
|
||||
// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
/// A structure representing BrandId[15:0] from
|
||||
/// CPUID Fn8000_0001_EBX
|
||||
typedef struct {
|
||||
UINT8 String1:4; ///< An index to a string value used to create the name string
|
||||
UINT8 String2:4; ///< An index to a string value used to create the name string
|
||||
UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
|
||||
UINT8 Model:7; ///< A field used to create the model number in the name string
|
||||
UINT8 Socket:4; ///< Specifies the package type
|
||||
UINT8 Cores:4; ///< Identifies how many physical cores are present
|
||||
} AMD_CPU_BRAND_DATA;
|
||||
|
||||
/// A structure containing string1 and string2 values
|
||||
/// as well as information pertaining to their usage
|
||||
typedef struct {
|
||||
IN UINT8 Cores; ///< Appropriate number of physical cores
|
||||
IN UINT8 Page; ///< This string's page number
|
||||
IN UINT8 Index; ///< String index
|
||||
IN UINT8 Socket; ///< Package type information
|
||||
IN CONST CHAR8 *Stringstart; ///< The literal string
|
||||
IN UINT8 Stringlength; ///< Number of characters in the string
|
||||
} AMD_CPU_BRAND;
|
||||
|
||||
/// An entire CPU brand table.
|
||||
typedef struct {
|
||||
UINT8 NumberOfEntries; ///< The number of entries in the table.
|
||||
CONST AMD_CPU_BRAND *Table; ///< The table entries.
|
||||
} CPU_BRAND_TABLE;
|
||||
|
||||
/**
|
||||
* Set down core register
|
||||
*
|
||||
* @CpuServiceInstances
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] Socket Socket ID.
|
||||
* @param[in] Module Module ID in socket.
|
||||
* @param[in] LeveledCores Number of core.
|
||||
* @param[in] CoreLevelMode Core level mode.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
* @retval TRUE Down Core register is updated.
|
||||
* @retval FALSE Down Core register is not updated.
|
||||
*/
|
||||
typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
|
||||
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
|
||||
IN UINT32 *Socket,
|
||||
IN UINT32 *Module,
|
||||
IN UINT32 *LeveledCores,
|
||||
IN CORE_LEVELING_TYPE CoreLevelMode,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/// Reference to a method
|
||||
typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
|
||||
|
||||
/**
|
||||
* Provide the interface to the Core Leveling Family Specific Services.
|
||||
*
|
||||
* Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
|
||||
* Each supported Family must provide an implementation for all methods in this interface, even if the
|
||||
* implementation is a CommonReturn().
|
||||
*/
|
||||
struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
|
||||
UINT16 Revision; ///< Interface version
|
||||
// Public Methods.
|
||||
PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------
|
||||
* F U N C T I O N P R O T O T Y P E
|
||||
*---------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// These are P U B L I C functions, used by IBVs
|
||||
AGESA_STATUS
|
||||
AmdCpuEarly (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig
|
||||
);
|
||||
|
||||
// These are P U B L I C functions, used by AGESA
|
||||
AGESA_STATUS
|
||||
PmInitializationAtEarly (
|
||||
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
VOID
|
||||
AmdCpuEarlyInitializer (
|
||||
IN AMD_CONFIG_PARAMS *StdHeader,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
|
||||
);
|
||||
|
||||
#endif // _CPU_EARLY_INIT_H_
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,200 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* FCH registers definition
|
||||
*
|
||||
*
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: FCH
|
||||
* @e \$Revision$ @e \$Date$
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#define KERN_FCH_SATA_DID 0x7900
|
||||
#define KERN_FCH_SATA_AHCI_DID 0x7901
|
||||
#define KERN_FCH_SATA_AMDAHCI_DID 0x7904
|
||||
|
||||
#define KERN_FCH_USB_XHCI_DID 0x7914 // Dev 0x10 Func 0
|
||||
#define KERN_FCH_USB_EHCI_DID 0x7908 // Dev 0x12 Func 0
|
||||
#define KERN_FCH_SMBUS_DID 0x790B // Dev 0x14 Func 0
|
||||
#define KERN_FCH_LPC_DID 0x790E // Dev 0x14 Func 3
|
||||
#define KERN_FCH_SD_DID 0x7906 // Dev 0x14 Func 7
|
||||
|
||||
#define KERN_EHCI1_BUS_DEV_FUN ((0x12 << 3) + 0)
|
||||
#define KERN_EHCI1_BUS 0
|
||||
#define KERN_EHCI1_DEV 18
|
||||
#define KERN_EHCI1_FUNC 0
|
||||
#define KERN_EHCI2_BUS_DEV_FUN ((0x13 << 3) + 0)
|
||||
#define KERN_EHCI2_BUS 0
|
||||
#define KERN_EHCI2_DEV 19
|
||||
#define KERN_EHCI2_FUNC 0
|
||||
#define KERN_EHCI3_BUS_DEV_FUN ((0x16 << 3) + 0)
|
||||
#define KERN_EHCI3_BUS 0
|
||||
#define KERN_EHCI3_DEV 22
|
||||
#define KERN_EHCI3_FUNC 0
|
||||
|
||||
// Specific FCH register for Kern
|
||||
#define FCH_EHCI_REG64 0x64
|
||||
#define FCH_EHCI_REGA4 0xA4
|
||||
|
||||
// HD Audio/Azalia
|
||||
#define KERN_EVENT_HD_AUDIO_MSI_ENABLE 0x02010100ul // HD Audio/Azalia MSI enable.
|
||||
#define KERN_EVENT_HD_AUDIO_DISABLE 0x02010101ul // HD Audio/Azalia Disable.
|
||||
#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC 0x02010102ul // HD Audio/Azalia Configure CODEC.
|
||||
#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC_BUSY 0x02010103ul // HD Audio/Azalia Configure CODEC Reset.
|
||||
#define KERN_ERROR_HD_AUDIO_RESET 0x02030100ul // HD Audio/Azalia Reset Failure.
|
||||
#define KERN_ERROR_HD_AUDIO_CODEC 0x02030101ul // HD Audio/Azalia Codec Not Found.
|
||||
// HW ACPI
|
||||
#define KERN_EVENT_HWACPI_PROG_ACPI_PMTBL 0x02010200ul // FCH program ACPI PM Controller Base Address.
|
||||
#define KERN_EVENT_HWACPI_PROG_ACPI_MMIO_IN_RESET 0x02010201ul // FCH program ACPIMMIO registers in RESET.
|
||||
#define KERN_EVENT_HWACPI_PROG_SCI_MAP 0x02010202ul // FCH program SCI map by OEM table (ACPIMMIO 0xFED803xx).
|
||||
#define KERN_EVENT_HWACPI_PROG_GPIO_MAP 0x02010203ul // FCH program GPIO setting by OEM table (ACPIMMIO 0xFED801xx).
|
||||
#define KERN_EVENT_HWACPI_PROG_SATA_PHY 0x02010204ul // FCH program SATA PHY by OEM table.
|
||||
#define KERN_EVENT_RTC_DAYLIGHT_SAVING_TIME 0x02010205ul // FCH RTC DayLight Saving Workaround.
|
||||
#define KERN_EVENT_RTC_CLEAR_BANK_SELECTION 0x02010206ul // FCH RTC clear BankSelection 0x0A Bit4 prevent error.
|
||||
#define KERN_EVENT_RTC_WA 0x02010207ul // FCH RTC workaround is set.
|
||||
#define KERN_EVENT_KBD_CONNECTED_THRU_USB 0x02010208ul // FCH IRQ1/IRQ12 connected to USB controller.
|
||||
#define KERN_EVENT_LEGACY_FREE_SET 0x02010209ul // FCH None Legacy IO setting.
|
||||
#define KERN_EVENT_ENABLED_ASF_REMOTE_CTRL 0x0201020Aul // FCH Enable ASF remote control function.
|
||||
#define KERN_EVENT_PCIEXP_WAKESTATUS_WA 0x0201020Bul // FCH PciExp Wake Status Workaround.
|
||||
#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL_IN_RESET 0x0201020Cul // FCH program OEM/Platform BIOS ACPIMMIO registers.
|
||||
#define KERN_EVENT_HWACPI_PROG_MMIOTBL 0x02010200ul // FCH program ACPIMMIO registers. (1st.)
|
||||
#define KERN_EVENT_HWACPI_NO_SIOKBC_ENABLE 0x02010201ul // FCH No SIO/KBC function is enabled.
|
||||
#define KERN_EVENT_HWACPI_NO_SIOKBC_DISABLE 0x02010202ul // FCH No SIO/KBC function is disabled.
|
||||
#define KERN_EVENT_HWACPI_PROG_SPECIFIC_MMIOTBL 0x02010203ul // FCH program Specific ACPIMMIO registers. (2nd.)
|
||||
#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL 0x02010204ul // FCH program OEM/Platform BIOS ACPIMMIO registers (3rd.)
|
||||
#define KERN_EVENT_HWACPI_SPREAD_SPECTRUM 0x02010205ul // FCH Enable Spread Spectrum function.
|
||||
#define KERN_EVENT_HWACPI_INT_CLK_SET 0x02010206ul // FCH Set Intermal Clock Display as 48Mhz.
|
||||
#define KERN_EVENT_HPET_TIMER_TICK_INTERVAL_WA_SET 0x02010207ul // FCH HPET timer tick interval workaround is set.
|
||||
#define KERN_EVENT_C1E_ENABLE 0x02010208ul // FCH C1e Enabled.
|
||||
#define KERN_EVENT_NATIVEPCIE_MODE_SET 0x02010208ul // FCH Native PCIe mode is set.
|
||||
#define KERN_ERROR_HPET_TBL_NOT_FOUND 0x02030200ul // FCH HPET Table does not found.
|
||||
// HWM
|
||||
#define KERN_EVENT_IMC_DISABLE 0x02010300ul // FCH HWM/IMC is disabled.
|
||||
#define KERN_EVENT_IMC_ENABLE 0x02010301ul // FCH HWM/IMC is enabled.
|
||||
// IMC
|
||||
#define KERN_EVENT_IMC_SW_TOGGLE_EVENT 0x02010302ul // FCH IMC Software Toggle Strapping. (IMC statement change)
|
||||
#define KERN_EVENT_EC_ENABLE 0x02020303ul // FCH EC enabled.
|
||||
#define KERN_EVENT_EC_KBD_ENABLE 0x02010304ul // FCH IMC EC KBD enabled.
|
||||
#define KERN_EVENT_EC_CHANNEL0_ENABLE 0x02010305ul // FCH IMC EC channel0 function enabled.
|
||||
#define KERN_EVENT_IMC_INTO_SLEEP_MODE 0x02010306ul // FCH IMC goes into sleep mode.
|
||||
#define KERN_EVENT_IMC_CRASH_RESET 0x02010307ul // FCH IMC Crash Reset to prevent repeating the reset forever.
|
||||
#define KERN_EVENT_IMC_SW_DISABLE_IMC 0x02010308ul // FCH Software disable IMC thru mailbox command.
|
||||
#define KERN_EVENT_IMC_DISABLE_SUREBOOT_TIMMER 0x02010309ul // FCH Disable SureBoot Timmer.
|
||||
#define KERN_EVENT_IMC_WAKEUP 0x0201030Aul // FCH IMC wakeup command.
|
||||
#define KERN_EVENT_IMC_IDLE 0x0201030Bul // FCH IMC idle command.
|
||||
#define KERN_EVENT_EC_DISABLE 0x0201030Cul // FCH EC disable by jumper setting or board config.
|
||||
#define KERN_ERROR_IMC_FW_VALIDATE_FAILED 0x02030300ul // FCH IMC firmware validation failure.
|
||||
// PCIE/AB
|
||||
#define KERN_EVENT_AB_SLOW_SPEED_ABLINK_CLOCK 0x02010400ul // FCH Set Low Speed AB link clock.
|
||||
#define KERN_EVENT_AB_RESET_CPU_ON_SYNC_FLOOD 0x02010401ul // FCH set AB reset CPU on sync flood enabled.
|
||||
#define KERN_EVENT_AB_CLOCK_GATING_ENABLE 0x02010402ul // FCH set AB Clock Gating function enabled.
|
||||
#define KERN_EVENT_AB_CLOCK_GATING_DISABLE 0x02010403ul // FCH set AB clock Gating function disabled.
|
||||
#define KERN_EVENT_AB_DMA_MEMORY_W3264B_ENABLE 0x02010404ul // FCH set AB DMA MEMORY Write 32/64B enabled.
|
||||
#define KERN_EVENT_AB_DMA_MEMORY_W3264B_DISABLED 0x02010405ul // FCH set AB DMA MEMORY Write 32/64B disabled.
|
||||
#define KERN_EVENT_AB_MEMORY_POWERSAVING_ENABLED 0x02010406ul // FCH Set AB Memory Power Saving enabled.
|
||||
#define KERN_EVENT_AB_MEMORY_POWERSAVING_DISABLED 0x02010407ul // FCH Set AB Memory Power Saving disabled.
|
||||
#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_ENABLED 0x02010408ul // FHC set ALink clock Gate-off enabled.
|
||||
#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_DISABLED 0x02010409ul // FHC set ALink clock Gate-off disabled.
|
||||
#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_ENABLED 0x0201040Aul // FHC set BLink clock Gate-off enabled.
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#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_DISABLED 0x0201040Bul // FHC set BLink clock Gate-off disabled.
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// SATA
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#define KERN_EVENT_SATA_ENABLE 0x02010500ul // FCH set SATA controller enabled.
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#define KERN_EVENT_SATA_MAX_GEN2_MODE_ENABLE 0x02010501ul // FCH set SATA support only Max. GEN2 mode.
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#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_EXT 0x02010502ul // FCH set SATA clock source as external 48Mhz.
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#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_INT 0x02010502ul // FCH set SATA clock source as internal 48Mhz.
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#define KERN_EVENT_SATA_SET_CLK_SOURCE_100_INT 0x02010503ul // FCH set SATA clock source as internal 100Mhz.
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#define KERN_EVENT_SATA_STABLE_MEM_SHUTDOWN_ENABLE 0x02010504ul // FCH set SATA stable memory sutdown enable * Misc.
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#define KERN_EVENT_SATA_PROG_SATA_PORT_PHY 0x02010505ul // FCH programming SATA port's PHY.
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#define KERN_EVENT_SATA_READ_SQUELCH_FROM_EFUSE 0x02010506ul // FCH programming SATA squelch value from eFuse.
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#define KERN_EVENT_SATA_DISABLE 0x02010507ul // FCH set SATA controller disabled.
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#define KERN_EVENT_SATA_AHCI_MODE 0x02010508ul // FCH set SATA as AHCI mode.
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||||
#define KERN_EVENT_SATA_IDE_2_AHCI_MODE 0x02010509ul // FCH set SATA as IDE_2_AHCI mode.
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||||
#define KERN_EVENT_SATA_IDE_MODE 0x0201050Aul // FCH set SATA as IDE mode.
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||||
#define KERN_EVENT_SATA_RAID_MODE 0x0201050Bul // FCH set SATA as RAID mode.
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||||
#define KERN_EVENT_SATA_MSI_CAP_ENABLE 0x0201050Cul // FCH set SATA MSI Capability Enabled.
|
||||
#define KERN_EVENT_SATA_SUPPORT_8_DEVICE 0x0201050Dul // FCH set SATA support 8 device mode.
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#define KERN_EVENT_SATA_DISABLED_GENERIC_MODE 0x0201050Eul // FCH set SATA disable generic mode.
|
||||
#define KERN_EVENT_SATA_PHY_PLL_SHUTDOWN 0x0201050Ful // FCH set SATA PHY PLL shutdown.
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#define KERN_EVENT_SATA_OOB_DETECTION_ENH 0x02010510ul // FCH set SATA OOB Detection Enhance Mode.
|
||||
#define KERN_EVENT_SATA_MEM_POWER_SAVING 0x02010511ul // FCH set SATA memory power saving.
|
||||
#define KERN_EVENT_SATA_DEV_SLP_PORT0 0x02010512ul // FCH set SATA Deep Sleep Mode on Port0.
|
||||
#define KERN_EVENT_SATA_DEV_SLP_PORT1 0x02010513ul // FCH set SATA Deep Sleep Mode on Port1.
|
||||
#define KERN_EVENT_SATA_AHCI_DIS_PREFETCH 0x02010514ul // FCH set SATA AHCI disable Prefetch.
|
||||
#define KERN_EVENT_SATA_PORT_MULT_CAP 0x02010515ul // FCH set SATA Port Mult Capability Enabled.
|
||||
#define KERN_EVENT_SATA_FIS_BASE_SWITCHING 0x02010516ul // FCH set SATA support FIS-based switching.
|
||||
#define KERN_EVENT_SATA_AGGR_LINK_PM_CAP 0x02010517ul // FCH set SATA aggressive link power management.
|
||||
#define KERN_EVENT_SATA_PSC_CAP 0x02010518ul // FCH set SATA support partial state.
|
||||
#define KERN_EVENT_SATA_SSC_CAP 0x02010519ul // FCH set SATA support Slumber mode.
|
||||
#define KERN_EVENT_SATA_CCC_CAP 0x0201051Aul // FCH set SATA support command completion coalescing.
|
||||
#define KERN_EVENT_SATA_AHCI_ENCLOSURE_MANAGEMENT 0x0201051Bul // FCH set SATA support Enclosure Management.
|
||||
#define KERN_EVENT_SATA_ESP_PORT_ENABLE 0x0201051Cul // FCH set SATA ESP ports (one of ESP ports are set).
|
||||
#define KERN_EVENT_SATA_BIOS_OS_HANDOFF 0x0201051Dul // FCH set SATA HBA supports the BIOS/OS handoff mechanism.
|
||||
#define KERN_EVENT_SATA_DRIVE_DETECTION 0x0201051Eul // FCH SATA is excuting SATA drive detection.
|
||||
#define KERN_EVENT_SATA_CLK_AUTO_OFF 0x0201051Ful // FCH set SATA Auto Clock off function.
|
||||
#define KERN_EVENT_SATA_PORT_GEN_MODE 0x02010520ul // FCH set SATA port GEN mode.
|
||||
#define KERN_EVENT_SATA_HOT_REMOVAL_ENH 0x02010521ul // FCH set SATA hot removal enhance mode.
|
||||
// SD
|
||||
#define KERN_EVENT_SD_ENABLE 0x02010600ul // FCH set SD controller to enable.
|
||||
#define KERN_EVENT_SD_AS_DMA_MODE 0x02010601ul // FCH set SD as DMA mode.
|
||||
#define KERN_EVENT_SD_AS_PIO_MODE 0x02010602ul // FCH set SD as PIO mode.
|
||||
#define KERN_EVENT_SD_AS_2_0_MODE 0x02010603ul // FCH set SD as 2.0 mode.
|
||||
#define KERN_EVENT_SD_AS_3_0_MODE 0x02010604ul // FCH set SD as 3.0 mode.
|
||||
#define KERN_EVENT_SD_CLOCK_MULTIPLIER 0x02010605ul // FCH set SD clock multiplier.
|
||||
#define KERN_EVENT_SD_DISABLE 0x02010606ul // FCH set SD controller to disable.
|
||||
// LPC/SPI
|
||||
#define KERN_EVENT_LPC_CLK0_DISABLE 0x02010700ul // FCH set LPC0 clock disabled.
|
||||
#define KERN_EVENT_LPC_CLK1_DISABLE 0x02010701ul // FCH set LPC1 clock disabled.
|
||||
#define KERN_EVENT_LPC_LEGACY_FREE_MODE 0x02010702ul // FCH set LPC as legacy free mode.
|
||||
#define KERN_EVENT_SPI_QUAL_MODE 0x02010703ul // FCH SPI Qual Mode is enabled (by user selection).
|
||||
#define KERN_EVENT_SPI_SPEED 0x02010704ul // FCH SPI speed is set by user selection.
|
||||
#define KERN_EVENT_SPI_FAST_SPEED 0x02010705ul // FCH SPI fast speed is set.
|
||||
#define KERN_EVENT_SPI_QUALIFY_QUAL_MODE 0x02010706ul // FCH SPI Qual Mode is validated.
|
||||
// USB
|
||||
#define KERN_ERROR_USB_ROMSIG_NOT_FOUND 0x02030800ul // FCH ROMSIG not found.
|
||||
#define KERN_ERROR_USB_XHCI_FW_FOUND 0x02030801ul // FCH XHCI firmware does not exist.
|
||||
#define KERN_EVENT_USB_EHCI1_ENABLE 0x02010800ul // FCH set EHCI1 enable.
|
||||
#define KERN_EVENT_USB_EHCI2_ENABLE 0x02010801ul // FCH set EHCI2 enable.
|
||||
#define KERN_EVENT_USB_EHCI3_ENABLE 0x02010802ul // FCH set EHCI3 enable.
|
||||
#define KERN_EVENT_USB_XHCI_DISABLE 0x02010803ul // FCH set XHCI disable.
|
||||
#define KERN_EVENT_USB_PHY_POWER_DOWN 0x02010804ul // FCH set USB PHY powerdown enable.
|
||||
#define KERN_EVENT_USB_PHY_CALIBRATED 0x02010805ul // FCH set USB PHY calibrated.
|
||||
#define KERN_EVENT_USB_PORT_PHY_SETTING 0x02010806ul // FCH set USB Port PHY setting.
|
||||
#define KERN_EVENT_USB_PORT_PHY_CLK_GATING 0x02010807ul // FCH set USB Port PHY Clock Gating.
|
||||
#define KERN_EVENT_USB_XHCI_USED_PREDEFINE_ADDRESS 0x02010808ul // FCH XHCI ROM location is used user-define address.
|
||||
#define KERN_EVENT_USB_XHCI_BOOTRAM_PRELOAD 0x02010809ul // FCH XHCI preload its BOOTRAM.
|
||||
#define KERN_EVENT_USB_XHCI_INSTRUCTRAM_PRELOAD 0x0201080Aul // FCH XHCI preload its InstructionRAM.
|
||||
#define KERN_EVENT_USB_XHCI_ROM_PREINIT_COMPLETED 0x0201080Bul // FCH XHCI preinit completed.
|
||||
#define KERN_EVENT_USB_XHCI0_ENABLE 0x0201080Cul // FCH set XHCI0 enable.
|
||||
#define KERN_EVENT_USB_XHCI1_ENABLE 0x0201080Dul // FCH set XHCI1 enable.
|
||||
Loading…
Reference in New Issue