Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADER
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
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@ -859,7 +859,7 @@ int elog_init(void)
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" shrink size %d\n", region_device_sz(&es->nv_dev),
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es->full_threshold, es->shrink_size);
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if (ENV_RAMSTAGE)
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if (ENV_PAYLOAD_LOADER)
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elog_add_boot_count();
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return 0;
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}
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@ -39,9 +39,13 @@
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#define ARCH_STAGE_HAS_BSS_SECTION 1
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#endif
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/* Default is that currently ramstage, smm, and rmodules have a heap. */
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/*
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* Default is that currently ENV_PAYLOAD_LOADER enable stage, smm,
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* and rmodules have a heap.
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*/
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#ifndef ARCH_STAGE_HAS_HEAP_SECTION
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#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
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#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \
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ENV_RMODULE)
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#endif
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#define STR(x) #x
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@ -277,7 +277,7 @@
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* be built with simple device model.
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*/
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#if (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR)
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#if (defined(__PRE_RAM__) || ENV_SMM || !ENV_PAYLOAD_LOADER)
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#define __SIMPLE_DEVICE__
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#endif
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@ -23,7 +23,7 @@ typedef unsigned int wint_t;
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/* The devicetree data structures are only mutable in ramstage. All other
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stages have a constant devicetree. */
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#if !ENV_RAMSTAGE
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#if !ENV_PAYLOAD_LOADER
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#define DEVTREE_EARLY 1
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#else
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#define DEVTREE_EARLY 0
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@ -307,7 +307,7 @@ void cbmem_get_region(void **baseptr, size_t *size)
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imd_region_used(cbmem_get_imd(), baseptr, size);
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}
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#if ENV_RAMSTAGE || (CONFIG(EARLY_CBMEM_LIST) \
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#if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \
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&& (ENV_POSTCAR || ENV_ROMSTAGE))
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/*
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* -fdata-sections doesn't work so well on read only strings. They all
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@ -47,7 +47,7 @@ static struct range_entry *alloc_range(struct memranges *ranges)
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range_entry_unlink(&ranges->free_list, r);
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return r;
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}
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if (ENV_RAMSTAGE)
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if (ENV_PAYLOAD_LOADER)
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return malloc(sizeof(struct range_entry));
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return NULL;
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}
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@ -160,7 +160,7 @@ fail:
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die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n");
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}
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#ifdef __RAMSTAGE__ // gc-sections should take care of this
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#if ENV_PAYLOAD_LOADER // gc-sections should take care of this
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static struct prog global_payload =
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PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload");
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@ -116,8 +116,11 @@ static struct timestamp_table *timestamp_alloc_cbmem_table(void)
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* based x86 platforms. */
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static int timestamp_should_run(void)
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{
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/* Only check boot_cpu() in other stages than ramstage on x86. */
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if ((!ENV_RAMSTAGE && CONFIG(ARCH_X86)) && !boot_cpu())
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/*
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* Only check boot_cpu() in other stages than
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* ENV_PAYLOAD_LOADER on x86.
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*/
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if ((!ENV_PAYLOAD_LOADER && CONFIG(ARCH_X86)) && !boot_cpu())
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return 0;
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return 1;
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@ -302,8 +305,8 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery)
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if (ts_cbmem_table->base_time == 0)
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ts_cbmem_table->base_time = ts_cache_table->base_time;
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/* Seed the timestamp tick frequency in ramstage. */
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if (ENV_RAMSTAGE)
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/* Seed the timestamp tick frequency in ENV_PAYLOAD_LOADER. */
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if (ENV_PAYLOAD_LOADER)
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ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz();
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/* Cache no longer required. */
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@ -249,7 +249,7 @@ void fast_spi_cache_bios_region(void)
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bios_size = ALIGN_UP(bios_size, alignment);
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base = 4ULL*GiB - bios_size;
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if (ENV_RAMSTAGE) {
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if (ENV_PAYLOAD_LOADER) {
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mtrr_use_temp_range(base, bios_size, type);
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} else {
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int mtrr = get_free_var_mtrr();
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@ -47,7 +47,7 @@ uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
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return EARLY_I2C_BASE(bus);
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}
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#if !ENV_RAMSTAGE
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#if !ENV_PAYLOAD_LOADER
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static int lpss_i2c_early_init_bus(unsigned int bus)
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{
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const struct dw_i2c_bus_config *config;
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@ -289,7 +289,7 @@ void pch_enable_lpc(void)
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soc_get_gen_io_dec_range(dev, gen_io_dec);
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lpc_set_gen_decode_range(gen_io_dec);
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soc_setup_dmi_pcr_io_dec(gen_io_dec);
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if (ENV_RAMSTAGE)
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if (ENV_PAYLOAD_LOADER)
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pch_lpc_interrupt_init();
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}
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