soc/intel/broadwell: implement RMRR ACPI table
Modeled after Skylake implementation; uses duplicated intel common SA functions to get RMRR addresses Test: build/boot purism/librem13v1, observe IOMMU fully functional with intel_iommu=on kernel parameter Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -590,12 +590,20 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
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if (igfx_dev && igfx_dev->enabled && gfxvtbar
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&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
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const unsigned long tmp = current;
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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/* Add RMRR entry */
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tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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}
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/* VTVC0BAR has to be set, enabled, and in 32-bit space */
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@ -137,4 +137,7 @@
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/* System Agent identification */
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u8 systemagent_revision(void);
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uintptr_t sa_get_tolud_base(void);
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uintptr_t sa_get_gsm_base(void);
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#endif
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@ -36,6 +36,18 @@ u8 systemagent_revision(void)
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return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
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}
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uintptr_t sa_get_tolud_base(void)
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{
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/* Bit 0 is lock bit, not part of address */
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return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1;
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}
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uintptr_t sa_get_gsm_base(void)
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{
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/* Bit 0 is lock bit, not part of address */
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return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1;
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}
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static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
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u32 *len)
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{
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