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Support for Fintek F71863FG. This might need some work on the copyright 

notices. Getting it into the tree so people can get to it.

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Wang Qing Pei 2010-08-17 15:05:05 +00:00 committed by Stefan Reinauer
parent acc3749644
commit 42e7c32cc5
7 changed files with 241 additions and 0 deletions
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2
src/superio/fintek/Kconfig
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config SUPERIO_FINTEK_F71805F config SUPERIO_FINTEK_F71805F
bool bool
config SUPERIO_FINTEK_F71863FG
bool

1
src/superio/fintek/Makefile.inc
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subdirs-y += f71805f subdirs-y += f71805f
subdirs-y += f71863fg

22
src/superio/fintek/f71863fg/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
obj-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.o

30
src/superio/fintek/f71863fg/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <uart8250.h>
/* This chip doesn't have keyboard and mouse support. */
extern struct chip_operations superio_fintek_f71863fg_ops;
struct superio_fintek_f71863fg_config {
struct uart8250 com1, com2;
};

29
src/superio/fintek/f71863fg/f71863fg.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Logical Device Numbers (LDN). */
#define F71863FG_FDC 0x00 /* Floppy */
#define F71863FG_SP1 0x01 /* UART1 */
#define F71863FG_SP2 0x02 /* UART2 */
#define F71863FG_PP 0x03 /* Parallel Port */
#define F71863FG_HWM 0x04 /* Hardware Monitor */
#define F71863FG_KBC 0x05 /* KBC devices */
#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */
#define F71863FG_PME 0x0a /* Power Management Events (PME) */

46
src/superio/fintek/f71863fg/f71863fg_early_serial.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Wang Qing Pei<wangqingpei@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */
#include <arch/romcc_io.h>
#include "f71863fg.h"
static inline void pnp_enter_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
outb(0x87, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
outb(0xaa, port);
}
static void f71863fg_enable_serial(device_t dev, unsigned int iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}

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src/superio/fintek/f71863fg/superio.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Wang Qing Pei<wangqingpei@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
#include <console/console.h>
#include <stdlib.h>
#include <uart8250.h>
#include "chip.h"
#include "f71863fg.h"
static void pnp_enter_conf_state(device_t dev)
{
outb(0x87, dev->path.pnp.port);
}
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}
static void f71863fg_init(device_t dev)
{
struct superio_fintek_f71863fg_config *conf = dev->chip_info;
struct resource *res0;
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case F71863FG_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case F71863FG_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
}
}
static void f71863fg_pnp_set_resources(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_resources(dev);
pnp_exit_conf_state(dev);
}
static void f71863fg_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_enable_resources(dev);
pnp_exit_conf_state(dev);
}
static void f71863fg_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
pnp_exit_conf_state(dev);
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = f71863fg_pnp_set_resources,
.enable_resources = f71863fg_pnp_enable_resources,
.enable = f71863fg_pnp_enable,
.init = f71863fg_init,
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F71863FG_GPIO, PNP_IRQ0, },
{ &ops, F71863FG_PME, },
};
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_fintek_f71863fg_ops = {
CHIP_NAME("Fintek F71863FG Super I/O")
.enable_dev = enable_dev
};