Improve comments in early SB600 setup, handle non-LPC strapping and
document verification against the data sheets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Maggie Li <maggie.li@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Carl-Daniel Hailfinger
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42f03e5647
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@ -53,11 +53,17 @@ static u8 get_sb600_revision()
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/***************************************
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* Legacy devices are mapped to LPC space.
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* serial port 0
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* Serial port 0
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* KBC Port
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* ACPI Micro-controller port
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* LPC ROM size,
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* LPC ROM size
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* This function does not change port 0x80 decoding.
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* Console output through any port besides 0x3f8 is unsupported.
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* If you use FWH ROMs, you have to setup IDSEL.
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* NOTE: Call me ASAP, because I will reset LPC ROM size!
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* Reviewed-by: Carl-Daniel Hailfinger
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* Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
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* (LPC ISA Bridge)
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***************************************/
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static void sb600_lpc_init(void)
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{
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@ -68,32 +74,42 @@ static void sb600_lpc_init(void)
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/* Enable lpc controller */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
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reg32 = pci_read_config32(dev, 0x64);
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reg32 |= 0x00100000;
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reg32 |= 1 << 20;
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pci_write_config32(dev, 0x64, reg32);
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dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
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/* Serial 0 */
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/* Decode port 0x3f8-0x3ff (Serial 0) */
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#warning Serial port decode on LPC is hardcoded to 0x3f8
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reg8 = pci_read_config8(dev, 0x44);
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reg8 |= (1 << 6);
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reg8 |= 1 << 6;
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pci_write_config8(dev, 0x44, reg8);
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/* PS/2 keyboard, ACPI */
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/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
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reg8 = pci_read_config8(dev, 0x47);
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reg8 |= (1 << 5) | (1 << 6);
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pci_write_config8(dev, 0x47, reg8);
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/* SuperIO, LPC ROM */
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reg8 = pci_read_config8(dev, 0x48);
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reg8 |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
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reg8 |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
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reg8 |= 1 << 6; /* enable for RTC I/O range */
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/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
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reg8 |= (1 << 1) | (1 << 0);
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/* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
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reg8 |= (1 << 3) | (1 << 4);
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/* Decode port 0x70-0x73 (RTC) */
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reg8 |= 1 << 6;
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pci_write_config8(dev, 0x48, reg8);
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/* hardware should enable LPC ROM by pin strapes */
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/* rom access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
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/* hardware should enable LPC ROM by pin straps */
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/* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
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/* See detail in BDG-215SB600-03.pdf page 15. */
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pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; */
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pci_write_config16(dev, 0x6c, 0xfff0); /* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB */
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/* enable LPC ROM range mirroring start 0x000e(0000) */
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pci_write_config16(dev, 0x68, 0x000e);
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/* enable LPC ROM range mirroring end 0x000f(ffff) */
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pci_write_config16(dev, 0x6a, 0x000f);
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/* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */
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pci_write_config16(dev, 0x6c, 0xfff0);
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/* enable LPC ROM range end at 0xffff(ffff) */
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pci_write_config16(dev, 0x6e, 0xffff);
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}
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/* what is its usage? */
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@ -201,26 +217,36 @@ static void sb600_pci_port80()
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/* P2P Bridge */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
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/* Chip Control: Enable subtractive decoding */
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 5;
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pci_write_config8(dev, 0x40, byte);
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/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 7;
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pci_write_config8(dev, 0x4B, byte);
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/* The same IO Base and IO Limit here is meaningful because we set the
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* bridge to be subtractive. During early setup stage, we have to make
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* sure that data can go through port 0x80.
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*/
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/* IO Base: 0xf000 */
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byte = pci_read_config8(dev, 0x1C);
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byte |= 0xF << 4;
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pci_write_config8(dev, 0x1C, byte);
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/* IO Limit: 0xf000 */
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byte = pci_read_config8(dev, 0x1D);
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byte |= 0xF << 4;
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pci_write_config8(dev, 0x1D, byte);
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/* PCI Command: Enable IO response */
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byte = pci_read_config8(dev, 0x04);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x04, byte);
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/* LPC controller */
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dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
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byte = pci_read_config8(dev, 0x4A);
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@ -234,13 +260,13 @@ static void sb600_lpc_port80(void)
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device_t dev;
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u32 reg32;
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/* enable lpc controller */
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/* Enable LPC controller */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
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reg32 = pci_read_config32(dev, 0x64);
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reg32 |= 0x00100000; /* lpcEnable */
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pci_write_config32(dev, 0x64, reg32);
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/* enable prot80 LPC decode in pci function 3 configuration space. */
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
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byte = pci_read_config8(dev, 0x4a);
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byte |= 1 << 5; /* enable port 80 */
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