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memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 

This is in preparation of a larger heap. I went for 2MB because why not?

Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Patrick Georgi 2023-10-07 11:16:43 +02:00
parent c666a91611
commit 42f15054b1
18 changed files with 22 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/emulation/qemu-power9/memlayout.ld
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@ -30,5 +30,5 @@ SECTIONS
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
STACK(0xa000000, 32K) STACK(0xa000000, 32K)
#endif #endif
RAMSTAGE(0xa008000, 1M) RAMSTAGE(0xa008000, 2M)
} }

2
src/mainboard/emulation/spike-riscv/memlayout.ld
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@ -16,5 +16,5 @@ SECTIONS
/* hole at (START + 8M + 14K, 50K) */ /* hole at (START + 8M + 14K, 50K) */
ROMSTAGE(START + 8M + 64K, 128K) ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
RAMSTAGE(START + 8M + 200K, 256K) RAMSTAGE(START + 8M + 200K, 2M)
} }

4
src/soc/cavium/cn81xx/memlayout.ld
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@ -30,9 +30,9 @@ SECTIONS
SRAM_END(BOOTROM_OFFSET + 0x80000) SRAM_END(BOOTROM_OFFSET + 0x80000)
TTB(BOOTROM_OFFSET + 0x80000, 512K) TTB(BOOTROM_OFFSET + 0x80000, 512K)
RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) RAMSTAGE(BOOTROM_OFFSET + 0x100000, 2M)
/* Stack for secondary CPUs */ /* Stack for secondary CPUs */
REGION(stack_sec, BOOTROM_OFFSET + 0x180000, REGION(stack_sec, BOOTROM_OFFSET + 0x300000,
CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000)
/* Leave some space for the payload */ /* Leave some space for the payload */

2
src/soc/mediatek/mt8173/memlayout.ld
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@ -42,5 +42,5 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M)
RAMSTAGE(0x40200000, 256K) RAMSTAGE(0x40200000, 2M)
} }

2
src/soc/mediatek/mt8183/memlayout.ld
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@ -44,7 +44,7 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M)
RAMSTAGE(0x40200000, 256K) RAMSTAGE(0x40200000, 2M)
BL31(0x54600000, 0x60000) BL31(0x54600000, 0x60000)
} }

2
src/soc/mediatek/mt8186/include/soc/memlayout.ld
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@ -62,7 +62,7 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M) POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 256K) RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000) BL31(0x54600000, 0x60000)
} }

2
src/soc/mediatek/mt8188/include/soc/memlayout.ld
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@ -66,7 +66,7 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M) POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 256K) RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000) BL31(0x54600000, 0x60000)
} }

2
src/soc/mediatek/mt8192/include/soc/memlayout.ld
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@ -54,7 +54,7 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M) POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 256K) RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000) BL31(0x54600000, 0x60000)
} }

2
src/soc/mediatek/mt8195/include/soc/memlayout.ld
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@ -65,7 +65,7 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M) DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M) POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 256K) RAMSTAGE(0x40300000, 2M)
BL31(0x54600000, 0x60000) BL31(0x54600000, 0x60000)
} }

2
src/soc/nvidia/tegra124/memlayout.ld
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@ -29,6 +29,6 @@ SECTIONS
DRAM_START(0x80000000) DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M) POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 128K) RAMSTAGE(0x80200000, 2M)
DMA_COHERENT(0x90000000, 2M) DMA_COHERENT(0x90000000, 2M)
} }

2
src/soc/nvidia/tegra210/memlayout.ld
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@ -32,6 +32,6 @@ SECTIONS
DRAM_START(0x80000000) DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M) POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 256K) RAMSTAGE(0x80200000, 2M)
TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
} }

4
src/soc/qualcomm/ipq40xx/memlayout.ld
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@ -44,6 +44,6 @@ SECTIONS
DRAM_START(0x80000000) DRAM_START(0x80000000)
SYMBOL(memlayout_cbmem_top, 0x87280000) SYMBOL(memlayout_cbmem_top, 0x87280000)
POSTRAM_CBFS_CACHE(0x87280000, 512K) POSTRAM_CBFS_CACHE(0x87280000, 512K)
RAMSTAGE(0x87300000, 512K) RAMSTAGE(0x87300000, 2M)
DMA_COHERENT(0x87400000, 2M) DMA_COHERENT(0x87500000, 2M)
} }

2
src/soc/qualcomm/ipq806x/memlayout.ld
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@ -32,7 +32,7 @@ SECTIONS
SRAM_END(0x2A060000) SRAM_END(0x2A060000)
DRAM_START(0x40000000) DRAM_START(0x40000000)
RAMSTAGE(0x40640000, 128K) RAMSTAGE(0x40640000, 2M)
SYMBOL(memlayout_cbmem_top, 0x59F80000) SYMBOL(memlayout_cbmem_top, 0x59F80000)
POSTRAM_CBFS_CACHE(0x59F80000, 384K) POSTRAM_CBFS_CACHE(0x59F80000, 384K)
DMA_COHERENT(0x5A000000, 2M) DMA_COHERENT(0x5A000000, 2M)

2
src/soc/qualcomm/qcs405/memlayout.ld
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@ -35,5 +35,5 @@ SECTIONS
/* DDR Carveout for BL31 usage */ /* DDR Carveout for BL31 usage */
REGION(dram_reserved, 0x85000000, 0x5100000, 4096) REGION(dram_reserved, 0x85000000, 0x5100000, 4096)
POSTRAM_CBFS_CACHE(0x9F800000, 384K) POSTRAM_CBFS_CACHE(0x9F800000, 384K)
RAMSTAGE(0x9F860000, 128K) RAMSTAGE(0x9F860000, 2M)
} }

2
src/soc/rockchip/rk3288/memlayout.ld
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@ -10,7 +10,7 @@
SECTIONS SECTIONS
{ {
DRAM_START(0x00000000) DRAM_START(0x00000000)
RAMSTAGE(0x00200000, 128K) RAMSTAGE(0x00200000, 2M)
POSTRAM_CBFS_CACHE(0x01000000, 1M) POSTRAM_CBFS_CACHE(0x01000000, 1M)
DMA_COHERENT(0x10000000, 2M) DMA_COHERENT(0x10000000, 2M)
FRAMEBUFFER(0x10800000, 8M) FRAMEBUFFER(0x10800000, 8M)

2
src/soc/samsung/exynos5250/memlayout.ld
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@ -27,7 +27,7 @@ SECTIONS
SRAM_END(0x2078000) SRAM_END(0x2078000)
DRAM_START(0x40000000) DRAM_START(0x40000000)
RAMSTAGE(0x40000000, 128K) RAMSTAGE(0x40000000, 2M)
POSTRAM_CBFS_CACHE(0x41000000, 8M) POSTRAM_CBFS_CACHE(0x41000000, 8M)
DMA_COHERENT(0x77300000, 1M) DMA_COHERENT(0x77300000, 1M)
} }

2
src/soc/samsung/exynos5420/memlayout.ld
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@ -28,7 +28,7 @@ SECTIONS
SRAM_END(0x2074000) SRAM_END(0x2074000)
DRAM_START(0x20000000) DRAM_START(0x20000000)
RAMSTAGE(0x20000000, 128K) RAMSTAGE(0x20000000, 2M)
POSTRAM_CBFS_CACHE(0x21000000, 8M) POSTRAM_CBFS_CACHE(0x21000000, 8M)
DMA_COHERENT(0x77300000, 1M) DMA_COHERENT(0x77300000, 1M)
} }

6
src/soc/sifive/fu540/memlayout.ld
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@ -22,7 +22,7 @@ SECTIONS
DRAM_START(FU540_DRAM) DRAM_START(FU540_DRAM)
REGION(opensbi, FU540_DRAM, 128K, 4K) REGION(opensbi, FU540_DRAM, 128K, 4K)
RAMSTAGE(FU540_DRAM + 128K, 256K) RAMSTAGE(FU540_DRAM + 128K, 2M)
MEM_STACK(FU540_DRAM + 448K, 20K) MEM_STACK(FU540_DRAM + 128K + 2M, 20K)
POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M)
} }