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ec/google/chromeec: Provide ec_sync wake option 

The ACPI spec defines keywords for the GpioInt and Interrupt resources
to specify whether a given pin is wake capable. Some boards are using
the ec sync interrupt pin to wake the system so the CREC _CRS needs to
be updated accordingly.

Provide a new macro that allows a board to specify whether its ec sync
pin is wake capable.

BUG=b:243700486
TEST=Dump ACPI and verify ExclusiveAndWake share type is set when
     EC_SYNC_IRQ_WAKE_CAPABLE is defined

Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
This commit is contained in:
Mark Hasemeyer 2023-11-29 15:42:03 -07:00 committed by Felix Held
parent f3523b4f0d
commit 431ca5eab5
1 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/ec/google/chromeec/acpi/cros_ec.asl
View File

@ -9,10 +9,17 @@ Device (CREC)
Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
#endif
#ifdef EC_SYNC_IRQ_WAKE_CAPABLE
#define EC_SYNC_SHARE_TYPE ExclusiveAndWake
#else
#define EC_SYNC_SHARE_TYPE Exclusive
#endif
#ifdef EC_ENABLE_SYNC_IRQ
Name (_CRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive)
Interrupt (ResourceConsumer, Level, ActiveLow,
EC_SYNC_SHARE_TYPE)
{
EC_SYNC_IRQ
}
@ -22,8 +29,8 @@ Device (CREC)
#ifdef EC_ENABLE_SYNC_IRQ_GPIO
Name (_CRS, ResourceTemplate ()
{
GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000,
"\\_SB.GPIO", 0x00, ResourceConsumer, ,)
GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault,
0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,)
{
EC_SYNC_IRQ
}