From 432ac615d018465e9808be4286c0caf2ca192cf1 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 13 Jun 2017 14:17:05 +0200
Subject: [PATCH] soc/intel/skylake: Don't allow user to change DCACHE base and
 size
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
 src/soc/intel/skylake/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 26f90218d7..fb2d94b974 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -127,11 +127,11 @@ config CPU_ADDR_BITS
 	default 36
 
 config DCACHE_RAM_BASE
-	hex "Base address of cache-as-RAM"
+	hex
 	default 0xfef00000
 
 config DCACHE_RAM_SIZE
-	hex "Length in bytes of cache-as-RAM"
+	hex
 	default 0x40000
 	help
 	  The size of the cache-as-ram region required during bootblock