From 433343eaaa987432242909fe4b1b482d53b66b4a Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 24 Apr 2023 15:50:15 -0700 Subject: [PATCH] soc/intel/alderlake: Hook up UPD LowerBasicMemTestSize Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718 Reviewed-by: Eric Lai Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Sridhar Siricilla --- src/soc/intel/alderlake/chip.h | 7 +++++++ src/soc/intel/alderlake/romstage/fsp_params.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b6b61cda13..f4cab6fe6a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -730,6 +730,13 @@ struct soc_intel_alderlake_config { * Set this to 1 in order to disable Tccold Handshake */ bool disable_dynamic_tccold_handshake; + + /* + * Enable or Disable Reduced BasicMemoryTest size. + * Default is set to 0. + * Set this to 1 in order to reduce BasicMemoryTest size + */ + bool lower_basic_mem_test_size; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 50343fb7a7..1326cb5c1a 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -158,6 +158,9 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrSpeedControl = 1; } +#if CONFIG(SOC_INTEL_RAPTORLAKE) + m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; +#endif } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,