mb/google/dedede/var/beadrix: Update SoC gpio pin of DMIC

Update SoC GPIO setting of unused DMIC channel according to beadrix
schematics.

GPP_S2 : NF2 -> NC (DMIC1_CLK)
GPP_S3 : NF2 -> NC (DMIC1_DATA)

BUG=b:203113413, b:237224862
BRANCH=None
TEST=on beadrix, validated by beadrix's DMIC working properly.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Teddy Shih 2022-06-24 16:13:00 +08:00 committed by Karthik Ramasubramanian
parent 4c7ee50072
commit 433810a577
1 changed files with 5 additions and 0 deletions

View File

@ -83,6 +83,11 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_H7, NONE),
/* H17 : WWAN_RST_L */
PAD_CFG_GPO(GPP_H17, 0, PLTRST),
/* S2 : DMIC1_CLK ==> NC */
PAD_NC(GPP_S2, NONE),
/* S3 : DMIC1_DATA ==> NC */
PAD_NC(GPP_S3, NONE),
};
static const struct pad_config lte_disable_pads[] = {