mb/google/dedede/var/beadrix: Update SoC gpio pin of DMIC
Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -83,6 +83,11 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H7, NONE),
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/* H17 : WWAN_RST_L */
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PAD_CFG_GPO(GPP_H17, 0, PLTRST),
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/* S2 : DMIC1_CLK ==> NC */
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PAD_NC(GPP_S2, NONE),
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/* S3 : DMIC1_DATA ==> NC */
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PAD_NC(GPP_S3, NONE),
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};
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static const struct pad_config lte_disable_pads[] = {
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