intel/apollolake: Fix whitespace issues
Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14368 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This commit is contained in:
Martin Roth
parent
59493717ad
commit
433e8d272d
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@ -17,100 +17,100 @@
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scope (\_SB.PCI0) {
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/* LPIO1 PWM */
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Device(PWM) {
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Name (_ADR, 0x001A0000)
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Name (_DDN, "Intel(R) PWM Controller")
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}
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/* LPIO1 PWM */
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Device(PWM) {
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Name (_ADR, 0x001A0000)
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Name (_DDN, "Intel(R) PWM Controller")
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}
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/* LPIO1 HS-UART #1 */
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Device(URT1) {
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Name (_ADR, 0x00180000)
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Name (_DDN, "Intel(R) HS-UART Controller #1")
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}
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/* LPIO1 HS-UART #1 */
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Device(URT1) {
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Name (_ADR, 0x00180000)
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Name (_DDN, "Intel(R) HS-UART Controller #1")
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}
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/* LPIO1 HS-UART #2 */
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Device(URT2) {
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Name (_ADR, 0x00180001)
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Name (_DDN, "Intel(R) HS-UART Controller #2")
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}
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/* LPIO1 HS-UART #2 */
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Device(URT2) {
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Name (_ADR, 0x00180001)
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Name (_DDN, "Intel(R) HS-UART Controller #2")
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}
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/* LPIO1 HS-UART #3 */
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Device(URT3) {
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Name (_ADR, 0x00180002)
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Name (_DDN, "Intel(R) HS-UART Controller #3")
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}
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/* LPIO1 HS-UART #3 */
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Device(URT3) {
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Name (_ADR, 0x00180002)
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Name (_DDN, "Intel(R) HS-UART Controller #3")
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}
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/* LPIO1 HS-UART #4 */
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Device(URT4) {
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Name (_ADR, 0x00180003)
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Name (_DDN, "Intel(R) HS-UART Controller #4")
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}
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/* LPIO1 HS-UART #4 */
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Device(URT4) {
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Name (_ADR, 0x00180003)
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Name (_DDN, "Intel(R) HS-UART Controller #4")
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}
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/* LPIO1 SPI */
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Device(SPI1) {
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Name (_ADR, 0x00190000)
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Name (_DDN, "Intel(R) SPI Controller #1")
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}
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/* LPIO1 SPI */
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Device(SPI1) {
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Name (_ADR, 0x00190000)
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Name (_DDN, "Intel(R) SPI Controller #1")
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}
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/* LPIO1 SPI #2 */
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Device(SPI2) {
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Name (_ADR, 0x00190001)
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Name (_DDN, "Intel(R) SPI Controller #2")
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}
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/* LPIO1 SPI #2 */
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Device(SPI2) {
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Name (_ADR, 0x00190001)
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Name (_DDN, "Intel(R) SPI Controller #2")
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}
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/* LPIO1 SPI #3 */
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Device(SPI3) {
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Name (_ADR, 0x00190002)
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Name (_DDN, "Intel(R) SPI Controller #3")
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}
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/* LPIO1 SPI #3 */
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Device(SPI3) {
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Name (_ADR, 0x00190002)
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Name (_DDN, "Intel(R) SPI Controller #3")
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}
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/* LPIO2 I2C #0 */
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Device(I2C0) {
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Name (_ADR, 0x00160000)
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Name (_DDN, "Intel(R) I2C Controller #0")
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}
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/* LPIO2 I2C #0 */
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Device(I2C0) {
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Name (_ADR, 0x00160000)
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Name (_DDN, "Intel(R) I2C Controller #0")
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}
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/* LPIO2 I2C #1 */
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Device(I2C1) {
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Name (_ADR, 0x00160001)
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Name (_DDN, "Intel(R) I2C Controller #1")
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}
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/* LPIO2 I2C #1 */
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Device(I2C1) {
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Name (_ADR, 0x00160001)
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Name (_DDN, "Intel(R) I2C Controller #1")
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}
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/* LPIO2 I2C #2 */
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Device(I2C2) {
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Name (_ADR, 0x00160002)
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Name (_DDN, "Intel(R) I2C Controller #2")
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}
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/* LPIO2 I2C #2 */
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Device(I2C2) {
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Name (_ADR, 0x00160002)
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Name (_DDN, "Intel(R) I2C Controller #2")
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}
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/* LPIO2 I2C #3 */
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Device(I2C3) {
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Name (_ADR, 0x00160003)
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Name (_DDN, "Intel(R) I2C Controller #3")
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}
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/* LPIO2 I2C #3 */
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Device(I2C3) {
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Name (_ADR, 0x00160003)
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Name (_DDN, "Intel(R) I2C Controller #3")
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}
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/* LPIO2 I2C #4 */
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Device(I2C4) {
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Name (_ADR, 0x00170000)
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Name (_DDN, "Intel(R) I2C Controller #4")
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}
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/* LPIO2 I2C #4 */
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Device(I2C4) {
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Name (_ADR, 0x00170000)
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Name (_DDN, "Intel(R) I2C Controller #4")
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}
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/* LPIO2 I2C #5 */
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Device(I2C5) {
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Name (_ADR, 0x00170001)
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Name (_DDN, "Intel(R) I2C Controller #5")
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}
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/* LPIO2 I2C #5 */
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Device(I2C5) {
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Name (_ADR, 0x00170001)
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Name (_DDN, "Intel(R) I2C Controller #5")
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}
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/* LPIO2 I2C #6 */
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Device(I2C6) {
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Name (_ADR, 0x00170002)
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Name (_DDN, "Intel(R) I2C Controller #6")
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}
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/* LPIO2 I2C #6 */
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Device(I2C6) {
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Name (_ADR, 0x00170002)
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Name (_DDN, "Intel(R) I2C Controller #6")
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}
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/* LPIO2 I2C #7 */
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Device(I2C7) {
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Name (_ADR, 0x00170003)
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Name (_DDN, "Intel(R) I2C Controller #7")
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}
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/* LPIO2 I2C #7 */
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Device(I2C7) {
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Name (_ADR, 0x00170003)
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Name (_DDN, "Intel(R) I2C Controller #7")
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}
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}
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@ -15,10 +15,10 @@
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* GNU General Public License for more details.
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*/
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Name(_HID, EISAID("PNP0A08")) /* PCIe */
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Name(_CID, EISAID("PNP0A03")) /* PCI */
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Name(_ADR, 0)
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Name(_BBN, 0)
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Name(_HID, EISAID("PNP0A08")) /* PCIe */
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Name(_CID, EISAID("PNP0A03")) /* PCI */
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Name(_ADR, 0)
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Name(_BBN, 0)
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Device (MCHC)
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{
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@ -81,51 +81,52 @@ Device (MCHC)
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NonCacheable, ReadWrite,
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0x00000000, 0x10000, 0x1ffff, 0x00000000,
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0x10000,,, PM02)
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})
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})
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/* Current Resource Settings */
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Method (_CRS, 0, Serialized)
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{
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/* Current Resource Settings */
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Method (_CRS, 0, Serialized)
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{
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/* Find PCI resource area in MCRS */
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CreateDwordField (MCRS, ^PM01._MIN, PMIN)
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CreateDwordField (MCRS, ^PM01._MAX, PMAX)
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CreateDwordField (MCRS, ^PM01._LEN, PLEN)
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/* Find PCI resource area in MCRS */
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CreateDwordField (MCRS, ^PM01._MIN, PMIN)
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CreateDwordField (MCRS, ^PM01._MAX, PMAX)
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CreateDwordField (MCRS, ^PM01._LEN, PLEN)
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/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
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And(^TLUD, 0xFFF00000, PMIN)
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/* Read MMCONF base */
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And(^MCNF, 0xF0000000, PMAX)
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/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
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And(^TLUD, 0xFFF00000, PMIN)
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/* Read MMCONF base */
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And(^MCNF, 0xF0000000, PMAX)
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/* Calculate PCI MMIO Length */
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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/* Calculate PCI MMIO Length */
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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/* Find GFX resource area in GCRS */
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CreateDwordField(MCRS, ^STOM._MIN, GMIN)
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CreateDwordField(MCRS, ^STOM._MAX, GMAX)
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CreateDwordField(MCRS, ^STOM._LEN, GLEN)
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/* Find GFX resource area in GCRS */
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CreateDwordField(MCRS, ^STOM._MIN, GMIN)
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CreateDwordField(MCRS, ^STOM._MAX, GMAX)
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CreateDwordField(MCRS, ^STOM._LEN, GLEN)
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/* Read BGSM */
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And(^BGSM, 0xFFF00000, GMIN)
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/* Read BGSM */
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And(^BGSM, 0xFFF00000, GMIN)
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/* Read TOLUD */
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And(^TLUD, 0xFFF00000, GMAX)
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Decrement(GMAX)
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Add(Subtract(GMAX, GMIN), 1, GLEN)
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/* Read TOLUD */
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And(^TLUD, 0xFFF00000, GMAX)
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Decrement(GMAX)
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Add(Subtract(GMAX, GMIN), 1, GLEN)
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/* Patch PM02 range based on Memory Size */
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CreateQwordField (MCRS, ^PM02._MIN, MMIN)
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CreateQwordField (MCRS, ^PM02._MAX, MMAX)
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CreateQwordField (MCRS, ^PM02._LEN, MLEN)
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/* Patch PM02 range based on Memory Size */
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CreateQwordField (MCRS, ^PM02._MIN, MMIN)
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CreateQwordField (MCRS, ^PM02._MAX, MMAX)
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CreateQwordField (MCRS, ^PM02._LEN, MLEN)
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Store (^TUUD, Local0)
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If (LLessEqual (Local0, 0x1000000000))
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{
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Store (0, MMIN)
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Store (0, MLEN)
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Store (^TUUD, Local0)
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If (LLessEqual (Local0, 0x1000000000))
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{
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Store (0, MMIN)
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Store (0, MLEN)
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}
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Subtract (Add (MMIN, MLEN), 1, MMAX)
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Return (MCRS)
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}
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Subtract (Add (MMIN, MLEN), 1, MMAX)
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Return (MCRS)
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}
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}
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@ -21,44 +21,43 @@ Method(_PRT)
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{
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Return(Package() {
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Package(){0x0000FFFF, 0, 0, NPK_INT},
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Package(){0x0000FFFF, 1, 0, PUNIT_INT},
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Package(){0x0002FFFF, 0, 0, GEN_INT},
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Package(){0x0003FFFF, 0, 0, IUNIT_INT},
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Package(){0x000DFFFF, 1, 0, PMC_INT},
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Package(){0x000EFFFF, 0, 0, AUDIO_INT},
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Package(){0x000FFFFF, 0, 0, CSE_INT},
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Package(){0x0011FFFF, 0, 0, ISH_INT},
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Package(){0x0012FFFF, 0, 0, SATA_INT},
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Package(){0x0013FFFF, 0, 0, PIRQA_INT},
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Package(){0x0013FFFF, 1, 0, PIRQB_INT},
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Package(){0x0013FFFF, 2, 0, PIRQC_INT},
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Package(){0x0013FFFF, 3, 0, PIRQD_INT},
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Package(){0x0014FFFF, 0, 0, PIRQB_INT},
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Package(){0x0014FFFF, 1, 0, PIRQC_INT},
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Package(){0x0014FFFF, 2, 0, PIRQD_INT},
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Package(){0x0014FFFF, 3, 0, PIRQA_INT},
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Package(){0x0015FFFF, 0, 0, XHCI_INT},
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Package(){0x0015FFFF, 1, 0, XDCI_INT},
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Package(){0x0016FFFF, 0, 0, I2C0_INT},
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Package(){0x0016FFFF, 1, 0, I2C1_INT},
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Package(){0x0016FFFF, 2, 0, I2C2_INT},
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Package(){0x0016FFFF, 3, 0, I2C3_INT},
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Package(){0x0017FFFF, 0, 0, I2C4_INT},
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Package(){0x0017FFFF, 1, 0, I2C5_INT},
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Package(){0x0017FFFF, 2, 0, I2C6_INT},
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Package(){0x0017FFFF, 3, 0, I2C7_INT},
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Package(){0x0018FFFF, 0, 0, UART0_INT},
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Package(){0x0018FFFF, 1, 0, UART1_INT},
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Package(){0x0018FFFF, 2, 0, UART2_INT},
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Package(){0x0018FFFF, 3, 0, UART3_INT},
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Package(){0x0019FFFF, 0, 0, SPI0_INT},
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Package(){0x0019FFFF, 1, 0, SPI1_INT},
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Package(){0x0019FFFF, 2, 0, SPI2_INT},
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Package(){0x001BFFFF, 0, 0, SDCARD_INT},
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Package(){0x001CFFFF, 0, 0, EMMC_INT},
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Package(){0x001EFFFF, 0, 0, SDIO_INT},
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Package(){0x001FFFFF, 1, 0, SMBUS_INT},
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}
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)
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Package(){0x0000FFFF, 0, 0, NPK_INT},
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Package(){0x0000FFFF, 1, 0, PUNIT_INT},
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Package(){0x0002FFFF, 0, 0, GEN_INT},
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Package(){0x0003FFFF, 0, 0, IUNIT_INT},
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Package(){0x000DFFFF, 1, 0, PMC_INT},
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Package(){0x000EFFFF, 0, 0, AUDIO_INT},
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Package(){0x000FFFFF, 0, 0, CSE_INT},
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Package(){0x0011FFFF, 0, 0, ISH_INT},
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Package(){0x0012FFFF, 0, 0, SATA_INT},
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Package(){0x0013FFFF, 0, 0, PIRQA_INT},
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Package(){0x0013FFFF, 1, 0, PIRQB_INT},
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Package(){0x0013FFFF, 2, 0, PIRQC_INT},
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Package(){0x0013FFFF, 3, 0, PIRQD_INT},
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Package(){0x0014FFFF, 0, 0, PIRQB_INT},
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Package(){0x0014FFFF, 1, 0, PIRQC_INT},
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Package(){0x0014FFFF, 2, 0, PIRQD_INT},
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Package(){0x0014FFFF, 3, 0, PIRQA_INT},
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Package(){0x0015FFFF, 0, 0, XHCI_INT},
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Package(){0x0015FFFF, 1, 0, XDCI_INT},
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Package(){0x0016FFFF, 0, 0, I2C0_INT},
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Package(){0x0016FFFF, 1, 0, I2C1_INT},
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Package(){0x0016FFFF, 2, 0, I2C2_INT},
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Package(){0x0016FFFF, 3, 0, I2C3_INT},
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Package(){0x0017FFFF, 0, 0, I2C4_INT},
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Package(){0x0017FFFF, 1, 0, I2C5_INT},
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Package(){0x0017FFFF, 2, 0, I2C6_INT},
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Package(){0x0017FFFF, 3, 0, I2C7_INT},
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Package(){0x0018FFFF, 0, 0, UART0_INT},
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Package(){0x0018FFFF, 1, 0, UART1_INT},
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Package(){0x0018FFFF, 2, 0, UART2_INT},
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Package(){0x0018FFFF, 3, 0, UART3_INT},
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Package(){0x0019FFFF, 0, 0, SPI0_INT},
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Package(){0x0019FFFF, 1, 0, SPI1_INT},
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Package(){0x0019FFFF, 2, 0, SPI2_INT},
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Package(){0x001BFFFF, 0, 0, SDCARD_INT},
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Package(){0x001CFFFF, 0, 0, EMMC_INT},
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Package(){0x001EFFFF, 0, 0, SDIO_INT},
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Package(){0x001FFFFF, 1, 0, SMBUS_INT},
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})
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}
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@ -15,15 +15,15 @@
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_INT_DEFINE_ASL_
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#define _SOC_INT_DEFINE_ASL_
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#ifndef _SOC_INT_DEFINE_ASL_
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#define _SOC_INT_DEFINE_ASL_
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#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
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#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
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#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
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#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
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#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
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#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
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#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
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#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
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#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
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#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
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#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
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#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
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#define NPK_INT 16
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#define PIRQA_INT 16
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#define PIRQB_INT 17
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@ -31,27 +31,26 @@
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#define SATA_INT 19
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#define GEN_INT 19
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#define PIRQD_INT 19
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#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
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#define SMBUS_INT 20 /* PIRQE */
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#define CSE_INT 20 /* PIRQE */
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#define IUNIT_INT 21 /* PIRQF */
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#define PUNIT_INT 24
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#define AUDIO_INT 25
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#define ISH_INT 26
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#define I2C0_INT 27
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#define I2C1_INT 28
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#define I2C2_INT 29
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#define I2C3_INT 30
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#define I2C4_INT 31
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#define I2C5_INT 32
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#define I2C6_INT 33
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#define I2C7_INT 34
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#define SPI0_INT 35
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||||
#define SPI1_INT 36
|
||||
#define SPI2_INT 37
|
||||
#define UFS_INT 38
|
||||
#define EMMC_INT 39
|
||||
#define SDIO_INT 42
|
||||
|
||||
#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
|
||||
#define SMBUS_INT 20 /* PIRQE */
|
||||
#define CSE_INT 20 /* PIRQE */
|
||||
#define IUNIT_INT 21 /* PIRQF */
|
||||
#define PUNIT_INT 24
|
||||
#define AUDIO_INT 25
|
||||
#define ISH_INT 26
|
||||
#define I2C0_INT 27
|
||||
#define I2C1_INT 28
|
||||
#define I2C2_INT 29
|
||||
#define I2C3_INT 30
|
||||
#define I2C4_INT 31
|
||||
#define I2C5_INT 32
|
||||
#define I2C6_INT 33
|
||||
#define I2C7_INT 34
|
||||
#define SPI0_INT 35
|
||||
#define SPI1_INT 36
|
||||
#define SPI2_INT 37
|
||||
#define UFS_INT 38
|
||||
#define EMMC_INT 39
|
||||
#define SDIO_INT 42
|
||||
|
||||
#endif /* _SOC_INT_DEFINE_ASL_ */
|
||||
|
|
@ -23,6 +23,6 @@
|
|||
void soc_fill_common_fadt(acpi_fadt_t * fadt);
|
||||
|
||||
unsigned long southbridge_write_acpi_tables(device_t device,
|
||||
unsigned long current, struct acpi_rsdp *rsdp);
|
||||
unsigned long current, struct acpi_rsdp *rsdp);
|
||||
|
||||
#endif /* _SOC_APOLLOLAKE_ACPI_H_ */
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ void lpss_console_uart_init(void)
|
|||
pci_write_config32(uart, PCI_COMMAND,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||||
|
||||
/* Take UART out of reset */
|
||||
/* Take UART out of reset */
|
||||
lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
|
||||
|
||||
/* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue