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mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUs 

Configure GPIOs for eMMC SKUs

BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22

Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This commit is contained in:
David Wu 2019-08-08 19:20:55 +08:00 committed by Furquan Shaikh
parent aa9aff7b81
commit 434a975b97
1 changed files with 46 additions and 0 deletions
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46
src/mainboard/google/hatch/variants/kindred/gpio.c
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@ -53,6 +53,47 @@ static const struct pad_config ssd_sku_gpio_table[] = {
PAD_CFG_GPI(GPP_H22, NONE, PLTRST), PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
}; };
static const struct pad_config emmc_sku_gpio_table[] = {
/* E1 : M2_SSD_PEDET ==> NC */
PAD_NC(GPP_E1, NONE),
/* E4 : M2_SSD_PE_WAKE_ODL ==> NC */
PAD_NC(GPP_E4, NONE),
/* E5 : SATA_DEVSLP1 ==> NC */
PAD_NC(GPP_E5, NONE),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
/* F11 : EMMC_CMD ==> EMMC_CMD */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* F20 : EMMC_RCLK ==> EMMC_RCLK */
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* F21 : EMMC_CLK ==> EMMC_CLK */
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
};
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* F3 : MEM_STRAP_3 */ /* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST), PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
@ -96,6 +137,11 @@ const struct pad_config *override_gpio_table(size_t *num)
*num = ARRAY_SIZE(ssd_sku_gpio_table); *num = ARRAY_SIZE(ssd_sku_gpio_table);
return ssd_sku_gpio_table; return ssd_sku_gpio_table;
} }
/* For eMMC SKU */
if (sku_id == 2 || sku_id == 4 || sku_id == 21 || sku_id == 22) {
*num = ARRAY_SIZE(emmc_sku_gpio_table);
return emmc_sku_gpio_table;
}
*num = ARRAY_SIZE(gpio_table); *num = ARRAY_SIZE(gpio_table);
return gpio_table; return gpio_table;
} }