soc/mediatek/mt8195: add power and power control for eDP

1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate.
2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel.
3. Add eDP power domain control.

BUG=b:189985956

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/include/soc/pll_common.h

@@ -70,6 +70,8 @@ int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
 void mt_pll_raise_cci_freq(u32 freq);
+void mt_pll_set_tvd_pll1_freq(u32 freq);
+void edp_mux_set_sel(u32 sel);
 
 enum fmeter_type {
 	FMETER_ABIST = 0,

src/soc/mediatek/mt8195/Makefile.inc

@@ -56,6 +56,7 @@ ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
+ramstage-y += ../common/pll.c pll.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += soc.c
 ramstage-y += ../common/sspm.c

src/soc/mediatek/mt8195/include/soc/spm.h

@@ -991,6 +991,12 @@ static const struct power_domain_data disp[] = {
 		.sram_pdn_mask = 0x1 << 8,
 		.sram_ack_mask = 0x1 << 12,
 	},
+	{
+		.pwr_con = &mtk_spm->edp_tx_pwr_con,
+		.pwr_sta_mask = 0x1 << 17,
+		.sram_pdn_mask = 0x1 << 8,
+		.sram_ack_mask = 0x1 << 12,
+	},
 };
 
 static const struct power_domain_data audio[] = {

src/soc/mediatek/mt8195/pll.c

@@ -773,6 +773,24 @@ void mt_pll_raise_cci_freq(u32 freq)
 	clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
 }
 
+void mt_pll_set_tvd_pll1_freq(u32 freq)
+{
+	/* disable tvdpll frequency output */
+	clrbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
+
+	/* set tvdpll frequency */
+	pll_set_rate(&plls[APMIXED_TVDPLL1], freq);
+
+	/* enable tvdpll frequency output */
+	setbits32(plls[APMIXED_TVDPLL1].reg, MT8195_PLL_EN);
+	udelay(PLL_EN_DELAY);
+}
+
+void edp_mux_set_sel(u32 sel)
+{
+	mux_set_sel(&muxes[TOP_EDP_SEL], sel);
+}
+
 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
 {
 	u32 output, count, clk_dbg_cfg, clk_misc_cfg_0;