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mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M 

Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.

However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.

For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.

BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().

Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2022-10-07 18:24:58 +02:00 committed by Martin L Roth
parent 036b16b884
commit 436f1c471a
1 changed files with 23 additions and 0 deletions
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23
src/mainboard/siemens/mc_apl1/bootblock.c
View File

@ -2,7 +2,26 @@
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <intelblocks/gpio.h>
#include <types.h>
static void pcie_rp_early_enable(void)
{
const pci_devfn_t rp_dev = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
if (pci_read_config16(rp_dev, PCI_VENDOR_ID) == 0xffff)
return;
/*
* Needs to be done "immediately after PERST# de-assertion"
* as per IAFW BIOS spec volume 2 (doc 559811)
*/
pci_and_config32(rp_dev, 0x338, ~(1 << 26)); /* BLKDQDA */
pci_and_config32(rp_dev, 0xf4, ~(1 << 2)); /* BLKPLLEN */
}
void bootblock_mainboard_early_init(void)
{
@ -11,4 +30,8 @@ void bootblock_mainboard_early_init(void)
pads = variant_early_gpio_table(&num);
gpio_configure_pads(pads, num);
/* Enable the PCIe root port when used before FSP-M MemoryInit() */
if (CONFIG(EARLY_PCI_BRIDGE))
pcie_rp_early_enable();
}