GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/octopus: Edge trigger cr50 interrupt 

Interrupts from cr50 are edge-triggered, not level-triggered. This
change updates the GPIO configuration accordingly.

BUG=b:75306520
BRANCH=None
TEST=None

Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Justin TerAvest 2018-04-05 14:56:23 -06:00 committed by Patrick Georgi
parent d58dd5c988
commit 438ca72460
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
@ -264,7 +264,7 @@ const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */ /* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */ DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */ /* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */