GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

x86: remove cpu_incs as romstage Make variable 

When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.

Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-09-02 22:23:11 -05:00
parent bc98cc66b2
commit 439356fabc
36 changed files with 36 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/x86/Makefile.inc
View File

@ -147,7 +147,6 @@ ifeq ($(CONFIG_SSE),y)
crt0s += $(src)/cpu/x86/sse_enable.inc crt0s += $(src)/cpu/x86/sse_enable.inc
endif endif
crt0s += $(cpu_incs)
crt0s += $(cpu_incs-y) crt0s += $(cpu_incs-y)
crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc

2
src/cpu/amd/agesa/Makefile.inc
View File

@ -27,7 +27,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c romstage-y += s3_resume.c
ramstage-y += s3_mtrr.c ramstage-y += s3_mtrr.c
cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
romstage-y += heapmanager.c romstage-y += heapmanager.c
ramstage-y += heapmanager.c ramstage-y += heapmanager.c

2
src/cpu/amd/geode_gx2/Makefile.inc
View File

@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
ramstage-y += geode_gx2_init.c ramstage-y += geode_gx2_init.c
ramstage-y += cpubug.c ramstage-y += cpubug.c
cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa

2
src/cpu/amd/geode_lx/Makefile.inc
View File

@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
ramstage-y += geode_lx_init.c ramstage-y += geode_lx_init.c
ramstage-y += cpubug.c ramstage-y += cpubug.c
cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa

2
src/cpu/amd/pi/Makefile.inc
View File

@ -25,7 +25,7 @@ romstage-y += s3_resume.c
ramstage-y += s3_resume.c ramstage-y += s3_resume.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_SPI_FLASH) += spi.c
cpu_incs += $(src)/cpu/amd/pi/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
romstage-y += heapmanager.c romstage-y += heapmanager.c
ramstage-y += heapmanager.c ramstage-y += heapmanager.c

2
src/cpu/amd/socket_754/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_939/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_940/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_AM2/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_AM2r2/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_AM3/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_ASB2/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_C32/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_F/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_F_1207/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/amd/socket_S1G1/Makefile.inc
View File

@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../smm subdirs-y += ../smm
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

2
src/cpu/intel/haswell/Makefile.inc
View File

@ -16,7 +16,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c smm-y += monotonic_timer.c
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
subdirs-y += ../../x86/tsc subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/mtrr

2
src/cpu/intel/model_106cx/Makefile.inc
View File

@ -1,5 +1,5 @@
ramstage-y += model_106cx_init.c ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c

2
src/cpu/intel/model_2065x/Makefile.inc
View File

@ -19,4 +19,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc

2
src/cpu/intel/model_206ax/Makefile.inc
View File

@ -8,4 +8,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc

2
src/cpu/intel/slot_1/Makefile.inc
View File

@ -32,4 +32,4 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc

2
src/cpu/intel/socket_BGA956/Makefile.inc
View File

@ -9,4 +9,4 @@ subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc

2
src/cpu/intel/socket_FC_PGA370/Makefile.inc
View File

@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc

2
src/cpu/intel/socket_LGA771/Makefile.inc
View File

@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc

2
src/cpu/intel/socket_PGA370/Makefile.inc
View File

@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc

2
src/cpu/intel/socket_mFCBGA479/Makefile.inc
View File

@ -6,4 +6,4 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc

2
src/cpu/intel/socket_mFCPGA478/Makefile.inc
View File

@ -11,4 +11,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc

2
src/cpu/intel/socket_mPGA479M/Makefile.inc
View File

@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc

2
src/cpu/via/c7/Makefile.inc
View File

@ -7,4 +7,4 @@ subdirs-y += ../../intel/microcode
ramstage-y += c7_init.c ramstage-y += c7_init.c
cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc

2
src/cpu/via/nano/Makefile.inc
View File

@ -30,4 +30,4 @@ ramstage-y += update_ucode.c
# the rest of coreboot. # the rest of coreboot.
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc

4
src/drivers/intel/fsp1_0/Makefile.inc
View File

@ -25,9 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y) cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
endif
ifeq ($(CONFIG_HAVE_FSP_BIN),y) ifeq ($(CONFIG_HAVE_FSP_BIN),y)
cbfs-files-y += fsp.bin cbfs-files-y += fsp.bin

2
src/mainboard/emulation/qemu-i440fx/Makefile.inc
View File

@ -1,3 +1,3 @@
cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += northbridge.c ramstage-y += northbridge.c
ramstage-y += fw_cfg.c ramstage-y += fw_cfg.c

2
src/mainboard/emulation/qemu-q35/Makefile.inc
View File

@ -1,3 +1,3 @@
cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += ../qemu-i440fx/northbridge.c
ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/fw_cfg.c

2
src/northbridge/intel/i5000/Makefile.inc
View File

@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)
ramstage-y += northbridge.c ramstage-y += northbridge.c
romstage-y += raminit.c romstage-y += raminit.c
cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S
endif endif

2
src/soc/intel/baytrail/romstage/Makefile.inc
View File

@ -1,4 +1,4 @@
cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += raminit.c romstage-y += raminit.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c

2
src/soc/intel/broadwell/romstage/Makefile.inc
View File

@ -1,4 +1,4 @@
cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
romstage-y += cpu.c romstage-y += cpu.c
romstage-y += pch.c romstage-y += pch.c