x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
parent
bc98cc66b2
commit
439356fabc
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@ -147,7 +147,6 @@ ifeq ($(CONFIG_SSE),y)
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crt0s += $(src)/cpu/x86/sse_enable.inc
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endif
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crt0s += $(cpu_incs)
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crt0s += $(cpu_incs-y)
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crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
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@ -27,7 +27,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-y += s3_resume.c
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ramstage-y += s3_mtrr.c
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cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
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romstage-y += heapmanager.c
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ramstage-y += heapmanager.c
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@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
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ramstage-y += geode_gx2_init.c
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ramstage-y += cpubug.c
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cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
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cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
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vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
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@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm
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ramstage-y += geode_lx_init.c
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ramstage-y += cpubug.c
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cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
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cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
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vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
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@ -25,7 +25,7 @@ romstage-y += s3_resume.c
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ramstage-y += s3_resume.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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cpu_incs += $(src)/cpu/amd/pi/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
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romstage-y += heapmanager.c
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ramstage-y += heapmanager.c
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm
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cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
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@ -16,7 +16,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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smm-y += monotonic_timer.c
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cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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@ -1,5 +1,5 @@
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ramstage-y += model_106cx_init.c
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subdirs-y += ../../x86/name
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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@ -19,4 +19,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
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@ -8,4 +8,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
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@ -32,4 +32,4 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -9,4 +9,4 @@ subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -6,4 +6,4 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -11,4 +11,4 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -7,4 +7,4 @@ subdirs-y += ../../intel/microcode
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ramstage-y += c7_init.c
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cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
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@ -30,4 +30,4 @@ ramstage-y += update_ucode.c
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# the rest of coreboot.
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
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@ -25,9 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
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CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
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ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
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cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
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endif
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cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
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ifeq ($(CONFIG_HAVE_FSP_BIN),y)
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cbfs-files-y += fsp.bin
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@ -1,3 +1,3 @@
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cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
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cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
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ramstage-y += northbridge.c
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ramstage-y += fw_cfg.c
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@ -1,3 +1,3 @@
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cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
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cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
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ramstage-y += ../qemu-i440fx/northbridge.c
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ramstage-y += ../qemu-i440fx/fw_cfg.c
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@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y)
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ramstage-y += northbridge.c
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romstage-y += raminit.c
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cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S
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cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S
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endif
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@ -1,4 +1,4 @@
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cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
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cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
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romstage-y += romstage.c
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romstage-y += raminit.c
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romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
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@ -1,4 +1,4 @@
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cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
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cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
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romstage-y += cpu.c
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romstage-y += pch.c
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