early mtrr for the p6

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/p6/earlymtrr.c

@@ -0,0 +1,108 @@
+#include <cpu/p6/mtrr.h>
+#include <cpu/p6/msr.h>
+
+static inline unsigned long read_cr0(void)
+{
+    unsigned long cr0;
+    asm volatile ("movl %%cr0, %0" : "=r" (cr0));
+    return cr0;
+}
+
+static inline void write_cr0(unsigned long cr0)
+{
+    asm volatile ("movl %0, %%cr0" : : "r" (cr0));
+}
+
+/* the fixed and variable MTTRs are power-up with random values,
+ * clear them to MTRR_TYPE_UNCACHEABLE for safty.
+ */
+
+static void early_mtrr_init(void)
+{
+	static const unsigned long mtrr_msrs[] = {
+		/* fixed mtrr */
+		0x250, 0x258, 0x259,
+		0x268, 0x269, 0x26A,
+		0x26B, 0x26C, 0x26D,
+		0x26E, 0x26F,
+		/* var mtrr */
+		0x200, 0x201, 0x202, 0x203,
+		0x204, 0x205, 0x206, 0x207,
+		0x208, 0x209, 0x20A, 0x20B,
+		0x20C, 0x20D, 0x20E, 0x20F,
+		/* NULL end of table */
+		0
+	};
+	msr_t msr;
+	const unsigned long *msr_addr;
+	unsigned long cr0;
+
+	print_err("Disabling cache\n");
+	/* Just to be sure, take all the steps to disable the cache.
+	 * This may not be needed, but C3's may...
+	 * Invalidate the cache */
+	asm volatile ("invd");
+
+	/* Disable the cache */
+	cr0 = read_cr0();
+	cr0 |= 0x40000000;
+	write_cr0(cr0);
+
+	/* Disable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000000;
+	wrmsr(0x2ff, msr);
+
+	/* Invalidate the cache again */
+	asm volatile ("invd");
+
+	print_err("Clearing mtrr\n");
+
+	/* Inialize all of the relevant msrs to 0 */
+	msr.lo = 0;
+	msr.hi = 0;
+	for(msr_addr = mtrr_msrs; *msr_addr; msr_addr++) {
+		wrmsr(*msr_addr, msr);
+	}
+
+	/* Enable caching for 0 - 128MB using variable mtrr */
+	msr = rdmsr(0x200);
+	msr.hi &= 0xfffffff0;
+	msr.hi |= 0x00000000;
+	msr.lo &= 0x00000f00;
+	msr.lo |= 0x00000006;
+	wrmsr(0x200, msr);
+
+	msr = rdmsr(0x201);
+	msr.hi &= 0xfffffff0;
+	msr.hi |= 0x0000000f;
+	msr.lo &= 0x000007ff;
+	msr.lo |= 0xf0000800;
+	wrmsr(0x201, msr);
+
+#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+	print_err("Setting XIP\n");
+	/* enable write through caching so we can do execute in place
+	 * on the flash rom.
+	 */
+	msr.hi = 0x00000000;
+	msr.lo = XIP_ROM_BASE | MTRR_TYPE_WRTHROUGH;
+	wrmsr(0x202, msr);
+	msr.hi = 0x0000000f;
+	msr.lo = ~(XIP_ROM_SIZE - 1) | 0x800;
+	wrmsr(0x203, msr);
+#endif
+
+	/* Set the default memory type and enable fixed and variable MTRRs 
+	 */
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(0x2ff, msr);
+
+	/* Enable the cache */
+	cr0 = read_cr0();
+	cr0 &= 0x9fffffff;
+	write_cr0(cr0);
+	print_err("Enabled the cache\n");
+}

src/cpu/p6/mtrr.c

@@ -31,6 +31,14 @@
 
 #define arraysize(x)   (sizeof(x)/sizeof((x)[0]))
 
+#ifdef k8
+# define ADDRESS_BITS 40
+#else
+# define ADDRESS_BITS 36
+#endif
+#define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
+#define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
+
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
 	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
@@ -91,12 +99,14 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
 	base.hi = basek >> 22;
 	base.lo  = basek << 10;
 
+       //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
+
 	if (sizek < 4*1024*1024) {
-		mask.hi = 0x0FF;
+		mask.hi = ADDRESS_MASK_HIGH;
 		mask.lo = ~((sizek << 10) -1);
 	}
 	else {
-		mask.hi = 0x0F & (~((sizek >> 22) -1));
+		mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
 		mask.lo = 0;
 	}