diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 7dd9f154ef..e9786f14eb 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -53,6 +53,9 @@ chip soc/intel/cannonlake
 	# Enable DDC for DDI port B
 	register "DdiPortBDdc" = "1"
 
+	register "LanWakeFromDeepSx" = "0"
+	register "WolEnableOverride" = "0"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9bba226e58..40d9f71eed 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -400,6 +400,10 @@ struct soc_intel_cannonlake_config {
 
 	/* Unlock all GPIO Pads */
 	uint8_t PchUnlockGpioPads;
+
+	/* Enable GBE wakeup */
+	uint8_t LanWakeFromDeepSx;
+	uint8_t WolEnableOverride;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 61d2520693..cc01d10fe8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -212,6 +212,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->DdiPortDDdc = config->DdiPortDDdc;
 	params->DdiPortFDdc = config->DdiPortFDdc;
 
+	/* WOL */
+	params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
+	params->PchPmWolEnableOverride = config->WolEnableOverride;
+
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;