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soc/amd: factor out fch_smbus_init 

Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-01 21:17:17 +01:00
parent 875e5aa96c
commit 43a5f88bb4
5 changed files with 23 additions and 28 deletions
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2
src/soc/amd/common/block/include/amdblocks/smbus.h
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@ -47,4 +47,6 @@
#define SMBSLVDAT 0xc #define SMBSLVDAT 0xc
#define SMBTIMING 0xe #define SMBTIMING 0xe
void fch_smbus_init(void);
#endif /* AMD_BLOCK_SMBUS_H */ #endif /* AMD_BLOCK_SMBUS_H */

1
src/soc/amd/common/block/smbus/Makefile.inc
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@ -1,5 +1,6 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y)
bootblock-y += smbus_early_fch.c
romstage-y += smbus.c romstage-y += smbus.c
ramstage-y += smbus.c ramstage-y += smbus.c
ramstage-y += sm.c ramstage-y += sm.c

20
src/soc/amd/common/block/smbus/smbus_early_fch.c Normal file
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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/smbus.h>
#include <soc/southbridge.h>
void fch_smbus_init(void)
{
/* 400 kHz smbus speed. */
const uint8_t smbus_speed = (66000000 / (400000 * 4));
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
smbus_write8(SMBTIMING, smbus_speed);
/* Clear all SMBUS status bits */
smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
}

14
src/soc/amd/picasso/southbridge.c
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@ -113,20 +113,6 @@ void sb_clk_output_48Mhz(void)
misc_write32(MISC_CLK_CNTL1, ctrl); misc_write32(MISC_CLK_CNTL1, ctrl);
} }
static void fch_smbus_init(void)
{
/* 400 kHz smbus speed. */
const uint8_t smbus_speed = (66000000 / (400000 * 4));
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
smbus_write8(SMBTIMING, smbus_speed);
/* Clear all SMBUS status bits */
smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
}
static void lpc_configure_decodes(void) static void lpc_configure_decodes(void)
{ {
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))

14
src/soc/amd/stoneyridge/southbridge.c
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@ -332,20 +332,6 @@ static void setup_misc(int *reboot)
} }
} }
static void fch_smbus_init(void)
{
/* 400 kHz smbus speed. */
const uint8_t smbus_speed = (66000000 / (400000 * 4));
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
smbus_write8(SMBTIMING, smbus_speed);
/* Clear all SMBUS status bits */
smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
}
/* Before console init */ /* Before console init */
void bootblock_fch_early_init(void) void bootblock_fch_early_init(void)
{ {