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Revert "mb/google/brya: Add romstage early graphics for brya" 

This reverts commit 96d9b75669.

Reason for revert: Merged out of order, broke tree

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jakub Czapiga 2023-01-04 17:31:03 +00:00
parent e45f70423e
commit 43b7e60e3e
3 changed files with 1 additions and 45 deletions
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1
src/mainboard/google/brya/Makefile.inc
View File

@ -4,7 +4,6 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage.c
romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c

13
src/mainboard/google/brya/gma-mainboard.ads
View File

@ -1,13 +0,0 @@
-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(eDP,
others => Disabled);
end GMA.Mainboard;

32
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
View File

@ -123,37 +123,7 @@ chip soc/intel/alderlake
}"
device domain 0 on
# The timing values can be derived from datasheet of display panel
# You can use EDID string to identify the type of display on the board
# use below command to get display info from EDID
# strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
# refer to display PRM document (Volume 2b: Command Reference: Registers)
# for more info on display control registers
# https://01.org/linuxgraphics/documentation/hardware-specification-prms
#+-----------------------------+---------------------------------------+-----+
#| Intel docs | devicetree.cb | eDP |
#+-----------------------------+---------------------------------------+-----+
#| Power up delay | `gpu_panel_power_up_delay` | T3 |
#+-----------------------------+---------------------------------------+-----+
#| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
#+-----------------------------+---------------------------------------+-----+
#| Power Down delay | `gpu_panel_power_down_delay` | T10 |
#+-----------------------------+---------------------------------------+-----+
#| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
#+-----------------------------+---------------------------------------+-----+
#| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
#+-----------------------------+---------------------------------------+-----+
device ref igpu on
register "panel_cfg" = "{
.up_delay_ms = 200,
.down_delay_ms = 50,
.cycle_delay_ms = 500,
.backlight_on_delay_ms = 1,
.backlight_off_delay_ms = 200,
.backlight_pwm_hz = 200,
}"
end
device ref igpu on end
device ref dtt on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end