Revert "mb/google/brya: Add romstage early graphics for brya"
This reverts commit 96d9b75669
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Reason for revert: Merged out of order, broke tree
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
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commit
43b7e60e3e
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@ -4,7 +4,6 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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@ -1,13 +0,0 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(eDP,
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others => Disabled);
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end GMA.Mainboard;
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@ -123,37 +123,7 @@ chip soc/intel/alderlake
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}"
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}"
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device domain 0 on
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device domain 0 on
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# The timing values can be derived from datasheet of display panel
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device ref igpu on end
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# You can use EDID string to identify the type of display on the board
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# use below command to get display info from EDID
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# strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
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# refer to display PRM document (Volume 2b: Command Reference: Registers)
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# for more info on display control registers
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# https://01.org/linuxgraphics/documentation/hardware-specification-prms
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#+-----------------------------+---------------------------------------+-----+
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#| Intel docs | devicetree.cb | eDP |
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#+-----------------------------+---------------------------------------+-----+
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#| Power up delay | `gpu_panel_power_up_delay` | T3 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power Down delay | `gpu_panel_power_down_delay` | T10 |
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#+-----------------------------+---------------------------------------+-----+
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#| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
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#+-----------------------------+---------------------------------------+-----+
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#| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
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#+-----------------------------+---------------------------------------+-----+
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device ref igpu on
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register "panel_cfg" = "{
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.up_delay_ms = 200,
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.down_delay_ms = 50,
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.cycle_delay_ms = 500,
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.backlight_on_delay_ms = 1,
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.backlight_off_delay_ms = 200,
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.backlight_pwm_hz = 200,
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}"
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end
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device ref dtt on end
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device ref dtt on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp1 on end
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