src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer 2022-03-07 04:34:52 +01:00
parent 2c423441c0
commit 43b7f41678
263 changed files with 6620 additions and 6622 deletions

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@ -276,7 +276,7 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current,
return current; return current;
/* AMD/ATI uses VFCT */ /* AMD/ATI uses VFCT */
if (device->vendor == PCI_VENDOR_ID_ATI) { if (device->vendor == PCI_VID_ATI) {
acpi_vfct_t *vfct; acpi_vfct_t *vfct;
current = ALIGN_UP(current, 8); current = ALIGN_UP(current, 8);

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@ -60,6 +60,6 @@ static struct device_operations aspeed_ast2050_ops = {
static const struct pci_driver aspeed_ast2050_driver __pci_driver = { static const struct pci_driver aspeed_ast2050_driver __pci_driver = {
.ops = &aspeed_ast2050_ops, .ops = &aspeed_ast2050_ops,
.vendor = PCI_VENDOR_ID_ASPEED, .vendor = PCI_VID_ASPEED,
.device = PCI_DEVICE_ID_ASPEED_AST2050_VGA, .device = PCI_DID_ASPEED_AST2050_VGA,
}; };

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@ -27,6 +27,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver bcm57xx_aspm_fixup __pci_driver = { static const struct pci_driver bcm57xx_aspm_fixup __pci_driver = {
.ops = &bcm57xx_aspm_fixup_ops, .ops = &bcm57xx_aspm_fixup_ops,
.vendor = PCI_VENDOR_ID_BROADCOM, .vendor = PCI_VID_BROADCOM,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -108,13 +108,13 @@ static struct device_operations bh720_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_O2_BH720, PCI_DID_O2_BH720,
0 0
}; };
static const struct pci_driver bayhub_bh720 __pci_driver = { static const struct pci_driver bayhub_bh720 __pci_driver = {
.ops = &bh720_ops, .ops = &bh720_ops,
.vendor = PCI_VENDOR_ID_O2, .vendor = PCI_VID_O2,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -70,13 +70,13 @@ static struct device_operations lv2_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_O2_LV2, PCI_DID_O2_LV2,
0 0
}; };
static const struct pci_driver bayhub_lv2 __pci_driver = { static const struct pci_driver bayhub_lv2 __pci_driver = {
.ops = &lv2_ops, .ops = &lv2_ops,
.vendor = PCI_VENDOR_ID_O2, .vendor = PCI_VID_O2,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -35,13 +35,13 @@ static struct device_operations gl9750_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9750, PCI_DID_GLI_9750,
0 0
}; };
static const struct pci_driver genesyslogic_gl9750 __pci_driver = { static const struct pci_driver genesyslogic_gl9750 __pci_driver = {
.ops = &gl9750_ops, .ops = &gl9750_ops,
.vendor = PCI_VENDOR_ID_GLI, .vendor = PCI_VID_GLI,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -47,13 +47,13 @@ static struct device_operations gl9755_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9755, PCI_DID_GLI_9755,
0 0
}; };
static const struct pci_driver genesyslogic_gl9755 __pci_driver = { static const struct pci_driver genesyslogic_gl9755 __pci_driver = {
.ops = &gl9755_ops, .ops = &gl9755_ops,
.vendor = PCI_VENDOR_ID_GLI, .vendor = PCI_VID_GLI,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -50,13 +50,13 @@ static struct device_operations gl9763e_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9763E, PCI_DID_GLI_9763E,
0 0
}; };
static const struct pci_driver genesyslogic_gl9763e __pci_driver = { static const struct pci_driver genesyslogic_gl9763e __pci_driver = {
.ops = &gl9763e_ops, .ops = &gl9763e_ops,
.vendor = PCI_VENDOR_ID_GLI, .vendor = PCI_VID_GLI,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -159,7 +159,7 @@ static enum cb_err locate_vbt_vbios(const u8 *vbios, struct region_device *rdev)
/* Make sure we got an Intel VGA option rom */ /* Make sure we got an Intel VGA option rom */
if ((oprom->signature != OPROM_SIGNATURE) || if ((oprom->signature != OPROM_SIGNATURE) ||
(pcir->vendor != PCI_VENDOR_ID_INTEL) || (pcir->vendor != PCI_VID_INTEL) ||
(pcir->signature != 0x52494350) || (pcir->signature != 0x52494350) ||
(pcir->classcode[0] != 0x00) || (pcir->classcode[0] != 0x00) ||
(pcir->classcode[1] != 0x00) || (pcir->classcode[1] != 0x00) ||

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@ -224,6 +224,6 @@ static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 };
static const struct pci_driver i210_driver __pci_driver = { static const struct pci_driver i210_driver __pci_driver = {
.ops = &i210_ops, .ops = &i210_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = i210_device_ids, .devices = i210_device_ids,
}; };

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@ -51,16 +51,16 @@ static const struct device_operations pci_ish_device_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CNL_ISHB, PCI_DID_INTEL_CNL_ISHB,
PCI_DEVICE_ID_INTEL_CML_ISHB, PCI_DID_INTEL_CML_ISHB,
PCI_DEVICE_ID_INTEL_TGL_ISHB, PCI_DID_INTEL_TGL_ISHB,
PCI_DEVICE_ID_INTEL_TGL_H_ISHB, PCI_DID_INTEL_TGL_H_ISHB,
0 0
}; };
static const struct pci_driver ish_intel_driver __pci_driver = { static const struct pci_driver ish_intel_driver __pci_driver = {
.ops = &pci_ish_device_ops, .ops = &pci_ish_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -267,7 +267,7 @@ static void r8168_set_customized_led(struct device *dev, u16 io_base)
if (!config) if (!config)
return; return;
if (dev->device == PCI_DEVICE_ID_REALTEK_8125) { if (dev->device == PCI_DID_REALTEK_8125) {
/* Set LED global Feature register */ /* Set LED global Feature register */
outb(config->led_feature, io_base + CMD_LED_FEATURE); outb(config->led_feature, io_base + CMD_LED_FEATURE);
printk(BIOS_DEBUG, "r8125: read back LED global feature setting as 0x%x\n", printk(BIOS_DEBUG, "r8125: read back LED global feature setting as 0x%x\n",
@ -425,14 +425,14 @@ static struct device_operations r8168_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_REALTEK_8168, PCI_DID_REALTEK_8168,
PCI_DEVICE_ID_REALTEK_8125, PCI_DID_REALTEK_8125,
0 0
}; };
static const struct pci_driver r8168_driver __pci_driver = { static const struct pci_driver r8168_driver __pci_driver = {
.ops = &r8168_ops, .ops = &r8168_ops,
.vendor = PCI_VENDOR_ID_REALTEK, .vendor = PCI_VID_REALTEK,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -53,7 +53,7 @@ static const unsigned short pci_device_ids[] = { 0xe822, 0xe823, 0 };
static const struct pci_driver rce822 __pci_driver = { static const struct pci_driver rce822 __pci_driver = {
.ops = &rce822_ops, .ops = &rce822_ops,
.vendor = PCI_VENDOR_ID_RICOH, .vendor = PCI_VID_RICOH,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -165,6 +165,6 @@ static const unsigned short nc_fpga_device_ids[] = { 0x4080, 0x4091, 0 };
static const struct pci_driver nc_fpga_driver __pci_driver = { static const struct pci_driver nc_fpga_driver __pci_driver = {
.ops = &nc_fpga_ops, .ops = &nc_fpga_ops,
.vendor = PCI_VENDOR_ID_SIEMENS, .vendor = PCI_VID_SIEMENS,
.devices = nc_fpga_device_ids, .devices = nc_fpga_device_ids,
}; };

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@ -17,7 +17,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0); pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0);
uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID); uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID);
if (id != (0x4091 << 16 | PCI_VENDOR_ID_SIEMENS)) if (id != (0x4091 << 16 | PCI_VID_SIEMENS))
return -1; return -1;
/* Setup base address for BAR0. */ /* Setup base address for BAR0. */

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@ -253,15 +253,15 @@ static const struct device_operations xhci_pci_ops = {
}; };
static const unsigned short amd_pci_device_ids[] = { static const unsigned short amd_pci_device_ids[] = {
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, PCI_DID_AMD_FAM17H_MODEL18H_XHCI0,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, PCI_DID_AMD_FAM17H_MODEL18H_XHCI1,
PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, PCI_DID_AMD_FAM17H_MODEL20H_XHCI0,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI, PCI_DID_AMD_FAM17H_MODEL60H_XHCI,
0 0
}; };
static const struct pci_driver xhci_pci_driver __pci_driver = { static const struct pci_driver xhci_pci_driver __pci_driver = {
.ops = &xhci_pci_ops, .ops = &xhci_pci_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = amd_pci_device_ids, .devices = amd_pci_device_ids,
}; };

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@ -470,7 +470,7 @@ static void emit_sar_acpi_structures(const struct device *dev)
* If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR
* ACPI tables are currently used only by Intel WiFi devices. * ACPI tables are currently used only by Intel WiFi devices.
*/ */
if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VENDOR_ID_INTEL) if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VID_INTEL)
return; return;
/* Retrieve the sar limits data */ /* Retrieve the sar limits data */

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@ -59,44 +59,44 @@ struct chip_operations drivers_wifi_generic_ops = {
}; };
static const unsigned short intel_pci_device_ids[] = { static const unsigned short intel_pci_device_ids[] = {
PCI_DEVICE_ID_1000_SERIES_WIFI, PCI_DID_1000_SERIES_WIFI,
PCI_DEVICE_ID_6005_SERIES_WIFI, PCI_DID_6005_SERIES_WIFI,
PCI_DEVICE_ID_6005_I_SERIES_WIFI, PCI_DID_6005_I_SERIES_WIFI,
PCI_DEVICE_ID_1030_SERIES_WIFI, PCI_DID_1030_SERIES_WIFI,
PCI_DEVICE_ID_6030_I_SERIES_WIFI, PCI_DID_6030_I_SERIES_WIFI,
PCI_DEVICE_ID_6030_SERIES_WIFI, PCI_DID_6030_SERIES_WIFI,
PCI_DEVICE_ID_6150_SERIES_WIFI, PCI_DID_6150_SERIES_WIFI,
PCI_DEVICE_ID_2030_SERIES_WIFI, PCI_DID_2030_SERIES_WIFI,
PCI_DEVICE_ID_2000_SERIES_WIFI, PCI_DID_2000_SERIES_WIFI,
PCI_DEVICE_ID_0135_SERIES_WIFI, PCI_DID_0135_SERIES_WIFI,
PCI_DEVICE_ID_0105_SERIES_WIFI, PCI_DID_0105_SERIES_WIFI,
PCI_DEVICE_ID_6035_SERIES_WIFI, PCI_DID_6035_SERIES_WIFI,
PCI_DEVICE_ID_5300_SERIES_WIFI, PCI_DID_5300_SERIES_WIFI,
PCI_DEVICE_ID_5100_SERIES_WIFI, PCI_DID_5100_SERIES_WIFI,
PCI_DEVICE_ID_6000_SERIES_WIFI, PCI_DID_6000_SERIES_WIFI,
PCI_DEVICE_ID_6000_I_SERIES_WIFI, PCI_DID_6000_I_SERIES_WIFI,
PCI_DEVICE_ID_5350_SERIES_WIFI, PCI_DID_5350_SERIES_WIFI,
PCI_DEVICE_ID_5150_SERIES_WIFI, PCI_DID_5150_SERIES_WIFI,
/* Wilkins Peak 2 */ /* Wilkins Peak 2 */
PCI_DEVICE_ID_WP_7260_SERIES_1_WIFI, PCI_DID_WP_7260_SERIES_1_WIFI,
PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI, PCI_DID_WP_7260_SERIES_2_WIFI,
/* Stone Peak 2 */ /* Stone Peak 2 */
PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI, PCI_DID_SP_7265_SERIES_1_WIFI,
PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI, PCI_DID_SP_7265_SERIES_2_WIFI,
/* Stone Field Peak */ /* Stone Field Peak */
PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI, PCI_DID_SFP_8260_SERIES_1_WIFI,
PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, PCI_DID_SFP_8260_SERIES_2_WIFI,
/* Windstorm Peak */ /* Windstorm Peak */
PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, PCI_DID_WSP_8275_SERIES_1_WIFI,
/* Thunder Peak 2 */ /* Thunder Peak 2 */
PCI_DEVICE_ID_TP_9260_SERIES_WIFI, PCI_DID_TP_9260_SERIES_WIFI,
/* Cyclone Peak */ /* Cyclone Peak */
PCI_DEVICE_ID_CyP_6SERIES_WIFI, PCI_DID_CyP_6SERIES_WIFI,
/* Typhoon Peak */ /* Typhoon Peak */
PCI_DEVICE_ID_TyP_6SERIES_WIFI, PCI_DID_TyP_6SERIES_WIFI,
/* Garfield Peak */ /* Garfield Peak */
PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, PCI_DID_GrP_6SERIES_1_WIFI,
PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, PCI_DID_GrP_6SERIES_2_WIFI,
0 0
}; };
@ -108,6 +108,6 @@ static const unsigned short intel_pci_device_ids[] = {
*/ */
static const struct pci_driver intel_wifi_pci_driver __pci_driver = { static const struct pci_driver intel_wifi_pci_driver __pci_driver = {
.ops = &wifi_pcie_ops, .ops = &wifi_pcie_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = intel_pci_device_ids, .devices = intel_pci_device_ids,
}; };

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@ -8,7 +8,7 @@
static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current)
{ {
if (dev->vendor != PCI_VENDOR_ID_INTEL) if (dev->vendor != PCI_VID_INTEL)
return 0; return 0;
struct smbios_type_intel_wifi { struct smbios_type_intel_wifi {

File diff suppressed because it is too large Load Diff

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@ -10,28 +10,28 @@
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, { PCI_DID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, { PCI_DID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 },
}; };
const struct system_power_limits sys_limits[] = { const struct system_power_limits sys_limits[] = {
/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, { PCI_DID_INTEL_ADL_P_ID_10, 15, 135 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 135 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 135 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 230 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, { PCI_DID_INTEL_ADL_P_ID_5, 45, 230 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, { PCI_DID_INTEL_ADL_P_ID_4, 45, 230 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 230 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, { PCI_DID_INTEL_ADL_P_ID_1, 45, 230 },
}; };
/* /*

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@ -6,11 +6,11 @@
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
/* All values are for baseline config as per bug:191906315 comment #10 */ /* All values are for baseline config as per bug:191906315 comment #10 */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
}; };
void variant_devtree_update(void) void variant_devtree_update(void)

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@ -6,11 +6,11 @@
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
/* All values are for baseline config as per bug:191906315 comment #10 */ /* All values are for baseline config as per bug:191906315 comment #10 */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
}; };
void variant_devtree_update(void) void variant_devtree_update(void)

View File

@ -5,10 +5,10 @@
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 },
}; };
void variant_devtree_update(void) void variant_devtree_update(void)

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@ -113,8 +113,8 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
psyspl2 = SET_PSYSPL2(watts); psyspl2 = SET_PSYSPL2(watts);
/* Limit PL2 if the adapter is with lower capability */ /* Limit PL2 if the adapter is with lower capability */
if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || if (mch_id == PCI_DID_INTEL_CML_ULT ||
mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) mch_id == PCI_DID_INTEL_CML_ULT_6_2)
pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2;
else else
pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2;
@ -134,11 +134,11 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
*/ */
volts_mv = BJ_VOLTS_MV; volts_mv = BJ_VOLTS_MV;
/* Use IGD ID to check if CPU is Core SKUs */ /* Use IGD ID to check if CPU is Core SKUs */
if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 &&
igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) {
psyspl2 = PUFF_CORE_CPU_PSYSPL2; psyspl2 = PUFF_CORE_CPU_PSYSPL2;
if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || if (mch_id == PCI_DID_INTEL_CML_ULT ||
mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) mch_id == PCI_DID_INTEL_CML_ULT_6_2)
pl2 = PUFF_U62_U42_PL2; pl2 = PUFF_U62_U42_PL2;
} }
} }

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@ -17,7 +17,7 @@ static uint32_t get_pl2(void)
id = pci_read_config16(igd_dev, PCI_DEVICE_ID); id = pci_read_config16(igd_dev, PCI_DEVICE_ID);
/* Assume we only have KLB-Y and AML-Y SKUs */ /* Assume we only have KLB-Y and AML-Y SKUs */
if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) if (id == PCI_DID_INTEL_KBL_GT2_SULXM)
return PL2_KBL; return PL2_KBL;
return PL2_AML; return PL2_AML;

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@ -18,7 +18,7 @@ static uint32_t get_pl2(void)
id = pci_read_config16(igd_dev, PCI_DEVICE_ID); id = pci_read_config16(igd_dev, PCI_DEVICE_ID);
/* Assume we only have KLB-Y and AML-Y SKUs */ /* Assume we only have KLB-Y and AML-Y SKUs */
if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) if (id == PCI_DID_INTEL_KBL_GT2_SULXM)
return PL2_KBL; return PL2_KBL;
return PL2_AML; return PL2_AML;

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@ -16,11 +16,11 @@
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */
/* PL2 values are for performance configuration */ /* PL2 values are for performance configuration */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
}; };
WEAK_DEV_PTR(dptf_policy); WEAK_DEV_PTR(dptf_policy);

View File

@ -48,7 +48,7 @@ static void mainboard_init(struct device *dev)
} }
/* Set SDHCI write protect polarity "SDWPPol" */ /* Set SDHCI write protect polarity "SDWPPol" */
sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); sdhci_dev = dev_find_device(PCI_VID_RICOH, PCI_DID_RICOH_R5C822, 0);
if (sdhci_dev) { if (sdhci_dev) {
if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
/* unlock */ /* unlock */

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@ -174,7 +174,7 @@ chip soc/intel/cannonlake
device pci 19.0 hidden end device pci 19.0 hidden end
chip soc/intel/common/block/uart chip soc/intel/common/block/uart
device pci 19.2 hidden device pci 19.2 hidden
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" register "devid" = "PCI_DID_INTEL_CNP_H_UART2"
end # UART #2, in ACPI mode end # UART #2, in ACPI mode
end end
device pci 1b.4 on # PCIe root port 21 (Slot 1) device pci 1b.4 on # PCIe root port 21 (Slot 1)

View File

@ -217,7 +217,7 @@ static void mainboard_final(void *chip_info)
/* Set Master Enable for on-board PCI device if allowed. */ /* Set Master Enable for on-board PCI device if allowed. */
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) { if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) { if (dev) {
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
} }

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@ -24,7 +24,7 @@ void variant_mainboard_final(void)
pcr_write16(PID_ITSS, 0x314c, 0x0321); pcr_write16(PID_ITSS, 0x314c, 0x0321);
/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
if (dev) if (dev)
pci_write_config8(dev, 0xd8, 0x3e); pci_write_config8(dev, 0xd8, 0x3e);

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@ -12,7 +12,7 @@ void variant_mainboard_final(void)
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) { if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
/* Set Master Enable for on-board PCI device if allowed. */ /* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
} }

View File

@ -37,7 +37,7 @@ void variant_mainboard_final(void)
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
/* Set Master Enable for on-board PCI device if allowed. */ /* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
@ -46,17 +46,17 @@ void variant_mainboard_final(void)
* XIO2001 PCIe to PCI Bridge. * XIO2001 PCIe to PCI Bridge.
*/ */
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x1d); pci_write_config8(parent, 0xd8, 0x1d);
} }
/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
* Bridge on this mainboard. * Bridge on this mainboard.
*/ */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) { if (dev) {
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3c); pci_write_config8(parent, 0xd8, 0x3c);
} }

View File

@ -44,7 +44,7 @@ void variant_mainboard_final(void)
pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
/* Set Master Enable for on-board PCI device if allowed. */ /* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
@ -52,17 +52,17 @@ void variant_mainboard_final(void)
/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe
* to PCI Bridge. */ * to PCI Bridge. */
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x0f); pci_write_config8(parent, 0xd8, 0x0f);
} }
/* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI
* Bridge on this mainboard. * Bridge on this mainboard.
*/ */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) { if (dev) {
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3e); pci_write_config8(parent, 0xd8, 0x3e);
} }
} }

View File

@ -37,7 +37,7 @@ void variant_mainboard_final(void)
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
/* Set Master Enable for on-board PCI device if allowed. */ /* Set Master Enable for on-board PCI device if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
@ -46,17 +46,17 @@ void variant_mainboard_final(void)
* XIO2001 PCIe to PCI Bridge. * XIO2001 PCIe to PCI Bridge.
*/ */
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x0F); pci_write_config8(parent, 0xd8, 0x0F);
} }
/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
* Bridge on this mainboard. * Bridge on this mainboard.
*/ */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) { if (dev) {
struct device *parent = dev->bus->dev; struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3c); pci_write_config8(parent, 0xd8, 0x3c);
} }

View File

@ -150,11 +150,11 @@ static void mainboard_final(void *chip_info)
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) { if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
/* Set Master Enable for on-board PCI devices if allowed. */ /* Set Master Enable for on-board PCI devices if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
if (dev) if (dev)
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) if (dev)
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
} }

View File

@ -791,7 +791,7 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver northbridge_driver __pci_driver = { static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = 0x1510, .device = 0x1510,
}; };

View File

@ -45,6 +45,6 @@ static struct device_operations iommu_ops = {
static const struct pci_driver iommu_driver __pci_driver = { static const struct pci_driver iommu_driver __pci_driver = {
.ops = &iommu_ops, .ops = &iommu_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU, .device = PCI_DID_AMD_15H_MODEL_101F_NB_IOMMU,
}; };

View File

@ -562,14 +562,14 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver family15_northbridge __pci_driver = { static const struct pci_driver family15_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT, .device = PCI_DID_AMD_15H_MODEL_101F_NB_HT,
}; };
static const struct pci_driver family10_northbridge __pci_driver = { static const struct pci_driver family10_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_10H_NB_HT, .device = PCI_DID_AMD_10H_NB_HT,
}; };
struct chip_operations northbridge_amd_agesa_family15tn_ops = { struct chip_operations northbridge_amd_agesa_family15tn_ops = {

View File

@ -556,14 +556,14 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver family16_northbridge __pci_driver = { static const struct pci_driver family16_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT, .device = PCI_DID_AMD_16H_MODEL_000F_NB_HT,
}; };
static const struct pci_driver family10_northbridge __pci_driver = { static const struct pci_driver family10_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_10H_NB_HT, .device = PCI_DID_AMD_10H_NB_HT,
}; };
static void fam16_finalize(void *chip_info) static void fam16_finalize(void *chip_info)

View File

@ -30,6 +30,6 @@ static struct device_operations iommu_ops = {
static const struct pci_driver iommu_driver __pci_driver = { static const struct pci_driver iommu_driver __pci_driver = {
.ops = &iommu_ops, .ops = &iommu_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU, .device = PCI_DID_AMD_16H_MODEL_303F_NB_IOMMU,
}; };

View File

@ -669,14 +669,14 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver family16_northbridge __pci_driver = { static const struct pci_driver family16_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, .device = PCI_DID_AMD_16H_MODEL_303F_NB_HT,
}; };
static const struct pci_driver family10_northbridge __pci_driver = { static const struct pci_driver family10_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_10H_NB_HT, .device = PCI_DID_AMD_10H_NB_HT,
}; };
static void fam16_finalize(void *chip_info) static void fam16_finalize(void *chip_info)

View File

@ -217,6 +217,6 @@ static const unsigned short pci_device_ids[] =
static const struct pci_driver gma __pci_driver = { static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -492,6 +492,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver pch_lpc __pci_driver = { static const struct pci_driver pch_lpc __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -97,6 +97,6 @@ static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 };
static const struct pci_driver haswell_minihd __pci_driver = { static const struct pci_driver haswell_minihd __pci_driver = {
.ops = &minihd_ops, .ops = &minihd_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -557,7 +557,7 @@ static const unsigned short mc_pci_device_ids[] = {
static const struct pci_driver mc_driver_hsw __pci_driver = { static const struct pci_driver mc_driver_hsw __pci_driver = {
.ops = &mc_ops, .ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = mc_pci_device_ids, .devices = mc_pci_device_ids,
}; };

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@ -170,6 +170,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver pch_pcie __pci_driver = { static const struct pci_driver pch_pcie __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -23,7 +23,7 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver northbridge_driver __pci_driver = { static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = 0x7190, .device = 0x7190,
}; };

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@ -767,12 +767,12 @@ static const unsigned short i945_gma_func1_ids[] = {
static const struct pci_driver i945_gma_func0_driver __pci_driver = { static const struct pci_driver i945_gma_func0_driver __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = i945_gma_func0_ids, .devices = i945_gma_func0_ids,
}; };
static const struct pci_driver i945_gma_func1_driver __pci_driver = { static const struct pci_driver i945_gma_func1_driver __pci_driver = {
.ops = &gma_func1_ops, .ops = &gma_func1_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = i945_gma_func1_ids, .devices = i945_gma_func1_ids,
}; };

View File

@ -150,7 +150,7 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver mc_driver __pci_driver = { static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops, .ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -208,6 +208,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver gma __pci_driver = { static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -215,7 +215,7 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver mc_driver_ilk __pci_driver = { static const struct pci_driver mc_driver_ilk __pci_driver = {
.ops = &mc_ops, .ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -280,6 +280,6 @@ static const unsigned short pci_device_ids[] =
static const struct pci_driver gma __pci_driver = { static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -660,6 +660,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver gma __pci_driver = { static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -389,7 +389,7 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver mc_driver __pci_driver = { static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops, .ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -64,6 +64,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver pch_pcie __pci_driver = { static const struct pci_driver pch_pcie __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -87,6 +87,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver gma __pci_driver = { static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops, .ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -101,29 +101,29 @@ void data_fabric_set_mmio_np(void)
static const char *data_fabric_acpi_name(const struct device *dev) static const char *data_fabric_acpi_name(const struct device *dev)
{ {
switch (dev->device) { switch (dev->device) {
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0: case PCI_DID_AMD_FAM17H_MODEL60H_DF0:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0: case PCI_DID_AMD_FAM19H_MODEL51H_DF0:
return "DFD0"; return "DFD0";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1: case PCI_DID_AMD_FAM17H_MODEL60H_DF1:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1: case PCI_DID_AMD_FAM19H_MODEL51H_DF1:
return "DFD1"; return "DFD1";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2: case PCI_DID_AMD_FAM17H_MODEL60H_DF2:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2: case PCI_DID_AMD_FAM19H_MODEL51H_DF2:
return "DFD2"; return "DFD2";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3: case PCI_DID_AMD_FAM17H_MODEL60H_DF3:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3: case PCI_DID_AMD_FAM19H_MODEL51H_DF3:
return "DFD3"; return "DFD3";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4: case PCI_DID_AMD_FAM17H_MODEL60H_DF4:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4: case PCI_DID_AMD_FAM19H_MODEL51H_DF4:
return "DFD4"; return "DFD4";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5: case PCI_DID_AMD_FAM17H_MODEL60H_DF5:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5: case PCI_DID_AMD_FAM19H_MODEL51H_DF5:
return "DFD5"; return "DFD5";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6: case PCI_DID_AMD_FAM17H_MODEL60H_DF6:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6: case PCI_DID_AMD_FAM19H_MODEL51H_DF6:
return "DFD6"; return "DFD6";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7: case PCI_DID_AMD_FAM17H_MODEL60H_DF7:
case PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7: case PCI_DID_AMD_FAM19H_MODEL51H_DF7:
return "DFD7"; return "DFD7";
default: default:
printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device);
@ -141,28 +141,28 @@ static struct device_operations data_fabric_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
/* Renoir DF devices */ /* Renoir DF devices */
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0, PCI_DID_AMD_FAM17H_MODEL60H_DF0,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1, PCI_DID_AMD_FAM17H_MODEL60H_DF1,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2, PCI_DID_AMD_FAM17H_MODEL60H_DF2,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3, PCI_DID_AMD_FAM17H_MODEL60H_DF3,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4, PCI_DID_AMD_FAM17H_MODEL60H_DF4,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5, PCI_DID_AMD_FAM17H_MODEL60H_DF5,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6, PCI_DID_AMD_FAM17H_MODEL60H_DF6,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7, PCI_DID_AMD_FAM17H_MODEL60H_DF7,
/* Cezanne DF devices */ /* Cezanne DF devices */
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0, PCI_DID_AMD_FAM19H_MODEL51H_DF0,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1, PCI_DID_AMD_FAM19H_MODEL51H_DF1,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2, PCI_DID_AMD_FAM19H_MODEL51H_DF2,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3, PCI_DID_AMD_FAM19H_MODEL51H_DF3,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4, PCI_DID_AMD_FAM19H_MODEL51H_DF4,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5, PCI_DID_AMD_FAM19H_MODEL51H_DF5,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6, PCI_DID_AMD_FAM19H_MODEL51H_DF6,
PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7, PCI_DID_AMD_FAM19H_MODEL51H_DF7,
0 0
}; };
static const struct pci_driver data_fabric_driver __pci_driver = { static const struct pci_driver data_fabric_driver __pci_driver = {
.ops = &data_fabric_ops, .ops = &data_fabric_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -225,6 +225,6 @@ static struct device_operations root_complex_operations = {
static const struct pci_driver family17_root_complex __pci_driver = { static const struct pci_driver family17_root_complex __pci_driver = {
.ops = &root_complex_operations, .ops = &root_complex_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB, .device = PCI_DID_AMD_17H_MODEL_606F_NB,
}; };

View File

@ -55,6 +55,6 @@ static struct device_operations acp_ops = {
static const struct pci_driver acp_driver __pci_driver = { static const struct pci_driver acp_driver __pci_driver = {
.ops = &acp_ops, .ops = &acp_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_FAM17H_ACP, .device = PCI_DID_AMD_FAM17H_ACP,
}; };

View File

@ -181,17 +181,17 @@ static const struct device_operations graphics_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU, PCI_DID_ATI_FAM17H_MODEL18H_GPU,
PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU, PCI_DID_ATI_FAM17H_MODEL60H_GPU,
PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU, PCI_DID_ATI_FAM17H_MODEL68H_GPU,
PCI_DEVICE_ID_ATI_FAM17H_MODELA0H_GPU, PCI_DID_ATI_FAM17H_MODELA0H_GPU,
PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE, PCI_DID_ATI_FAM19H_MODEL51H_GPU_CEZANNE,
PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_BARCELO, PCI_DID_ATI_FAM19H_MODEL51H_GPU_BARCELO,
0, 0,
}; };
static const struct pci_driver graphics_driver __pci_driver = { static const struct pci_driver graphics_driver __pci_driver = {
.ops = &graphics_ops, .ops = &graphics_ops,
.vendor = PCI_VENDOR_ID_ATI, .vendor = PCI_VID_ATI,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -9,9 +9,9 @@
#include <device/azalia_device.h> #include <device/azalia_device.h>
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DID_AMD_SB900_HDA,
PCI_DEVICE_ID_AMD_CZ_HDA, PCI_DID_AMD_CZ_HDA,
PCI_DEVICE_ID_AMD_FAM17H_HDA1, PCI_DID_AMD_FAM17H_HDA1,
0 0
}; };
@ -42,6 +42,6 @@ static struct device_operations hda_audio_ops = {
static const struct pci_driver hdaaudio_driver __pci_driver = { static const struct pci_driver hdaaudio_driver __pci_driver = {
.ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ? .ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ?
&default_azalia_audio_ops : &hda_audio_ops, &default_azalia_audio_ops : &hda_audio_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -39,16 +39,16 @@ static struct device_operations iommu_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, PCI_DID_AMD_15H_MODEL_303F_NB_IOMMU,
PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DID_AMD_15H_MODEL_707F_NB_IOMMU,
PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU, PCI_DID_AMD_17H_MODEL_1020_NB_IOMMU,
PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU, PCI_DID_AMD_17H_MODEL_606F_NB_IOMMU,
PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB_IOMMU, PCI_DID_AMD_17H_MODEL_A0AF_NB_IOMMU,
0 0
}; };
static const struct pci_driver iommu_driver __pci_driver = { static const struct pci_driver iommu_driver __pci_driver = {
.ops = &iommu_ops, .ops = &iommu_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -323,13 +323,13 @@ static struct device_operations lpc_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
/* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */
PCI_DEVICE_ID_AMD_SB900_LPC, PCI_DID_AMD_SB900_LPC,
/* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */
PCI_DEVICE_ID_AMD_CZ_LPC, PCI_DID_AMD_CZ_LPC,
0 0
}; };
static const struct pci_driver lpc_driver __pci_driver = { static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops, .ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -59,16 +59,16 @@ static struct device_operations internal_pcie_gpp_ops = {
}; };
static const unsigned short internal_pci_gpp_ids[] = { static const unsigned short internal_pci_gpp_ids[] = {
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC, PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC,
0 0
}; };
static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { static const struct pci_driver internal_pcie_gpp_driver __pci_driver = {
.ops = &internal_pcie_gpp_ops, .ops = &internal_pcie_gpp_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = internal_pci_gpp_ids, .devices = internal_pci_gpp_ids,
}; };
@ -83,15 +83,15 @@ static struct device_operations external_pcie_gpp_ops = {
}; };
static const unsigned short external_pci_gpp_ids[] = { static const unsigned short external_pci_gpp_ids[] = {
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1,
PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP, PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP,
0 0
}; };
static const struct pci_driver external_pcie_gpp_driver __pci_driver = { static const struct pci_driver external_pcie_gpp_driver __pci_driver = {
.ops = &external_pcie_gpp_ops, .ops = &external_pcie_gpp_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = external_pci_gpp_ids, .devices = external_pci_gpp_ids,
}; };

View File

@ -22,17 +22,17 @@ static struct device_operations sata_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DID_AMD_CZ_SATA,
PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, PCI_DID_AMD_CZ_SATA_AHCI,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0, PCI_DID_AMD_FAM17H_SATA_AHCI_VER0,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1, PCI_DID_AMD_FAM17H_SATA_AHCI_VER1,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0, PCI_DID_AMD_FAM17H_SATA_AHCI_RAID_VER0,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1, PCI_DID_AMD_FAM17H_SATA_AHCI_RAID_VER1,
0 0
}; };
static const struct pci_driver sata0_driver __pci_driver = { static const struct pci_driver sata0_driver __pci_driver = {
.ops = &sata_ops, .ops = &sata_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -88,7 +88,7 @@ static struct device_operations smbus_ops = {
static const struct pci_driver smbus_driver __pci_driver = { static const struct pci_driver smbus_driver __pci_driver = {
.ops = &smbus_ops, .ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
/* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */
.device = PCI_DEVICE_ID_AMD_CZ_SMBUS, .device = PCI_DID_AMD_CZ_SMBUS,
}; };

View File

@ -101,21 +101,21 @@ void data_fabric_set_mmio_np(void)
static const char *data_fabric_acpi_name(const struct device *dev) static const char *data_fabric_acpi_name(const struct device *dev)
{ {
switch (dev->device) { switch (dev->device) {
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0: case PCI_DID_AMD_FAM17H_MODEL18H_DF0:
return "DFD0"; return "DFD0";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1: case PCI_DID_AMD_FAM17H_MODEL18H_DF1:
return "DFD1"; return "DFD1";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2: case PCI_DID_AMD_FAM17H_MODEL18H_DF2:
return "DFD2"; return "DFD2";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3: case PCI_DID_AMD_FAM17H_MODEL18H_DF3:
return "DFD3"; return "DFD3";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4: case PCI_DID_AMD_FAM17H_MODEL18H_DF4:
return "DFD4"; return "DFD4";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5: case PCI_DID_AMD_FAM17H_MODEL18H_DF5:
return "DFD5"; return "DFD5";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6: case PCI_DID_AMD_FAM17H_MODEL18H_DF6:
return "DFD6"; return "DFD6";
case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7: case PCI_DID_AMD_FAM17H_MODEL18H_DF7:
return "DFD7"; return "DFD7";
default: default:
printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device);
@ -132,19 +132,19 @@ static struct device_operations data_fabric_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0, PCI_DID_AMD_FAM17H_MODEL18H_DF0,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1, PCI_DID_AMD_FAM17H_MODEL18H_DF1,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2, PCI_DID_AMD_FAM17H_MODEL18H_DF2,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3, PCI_DID_AMD_FAM17H_MODEL18H_DF3,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4, PCI_DID_AMD_FAM17H_MODEL18H_DF4,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5, PCI_DID_AMD_FAM17H_MODEL18H_DF5,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6, PCI_DID_AMD_FAM17H_MODEL18H_DF6,
PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7, PCI_DID_AMD_FAM17H_MODEL18H_DF7,
0 0
}; };
static const struct pci_driver data_fabric_driver __pci_driver = { static const struct pci_driver data_fabric_driver __pci_driver = {
.ops = &data_fabric_ops, .ops = &data_fabric_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -223,6 +223,6 @@ static struct device_operations root_complex_operations = {
static const struct pci_driver family17_root_complex __pci_driver = { static const struct pci_driver family17_root_complex __pci_driver = {
.ops = &root_complex_operations, .ops = &root_complex_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB, .device = PCI_DID_AMD_17H_MODEL_101F_NB,
}; };

View File

@ -104,21 +104,21 @@ void data_fabric_set_mmio_np(void)
static const char *data_fabric_acpi_name(const struct device *dev) static const char *data_fabric_acpi_name(const struct device *dev)
{ {
switch (dev->device) { switch (dev->device) {
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF0: case PCI_DID_AMD_FAM17H_MODELA0H_DF0:
return "DFD0"; return "DFD0";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF1: case PCI_DID_AMD_FAM17H_MODELA0H_DF1:
return "DFD1"; return "DFD1";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF2: case PCI_DID_AMD_FAM17H_MODELA0H_DF2:
return "DFD2"; return "DFD2";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF3: case PCI_DID_AMD_FAM17H_MODELA0H_DF3:
return "DFD3"; return "DFD3";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF4: case PCI_DID_AMD_FAM17H_MODELA0H_DF4:
return "DFD4"; return "DFD4";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF5: case PCI_DID_AMD_FAM17H_MODELA0H_DF5:
return "DFD5"; return "DFD5";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF6: case PCI_DID_AMD_FAM17H_MODELA0H_DF6:
return "DFD6"; return "DFD6";
case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF7: case PCI_DID_AMD_FAM17H_MODELA0H_DF7:
return "DFD7"; return "DFD7";
default: default:
printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device);
@ -135,19 +135,19 @@ static struct device_operations data_fabric_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF0, PCI_DID_AMD_FAM17H_MODELA0H_DF0,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF1, PCI_DID_AMD_FAM17H_MODELA0H_DF1,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF2, PCI_DID_AMD_FAM17H_MODELA0H_DF2,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF3, PCI_DID_AMD_FAM17H_MODELA0H_DF3,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF4, PCI_DID_AMD_FAM17H_MODELA0H_DF4,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF5, PCI_DID_AMD_FAM17H_MODELA0H_DF5,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF6, PCI_DID_AMD_FAM17H_MODELA0H_DF6,
PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF7, PCI_DID_AMD_FAM17H_MODELA0H_DF7,
0 0
}; };
static const struct pci_driver data_fabric_driver __pci_driver = { static const struct pci_driver data_fabric_driver __pci_driver = {
.ops = &data_fabric_ops, .ops = &data_fabric_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -227,6 +227,6 @@ static struct device_operations root_complex_operations = {
static const struct pci_driver family17_root_complex __pci_driver = { static const struct pci_driver family17_root_complex __pci_driver = {
.ops = &root_complex_operations, .ops = &root_complex_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.device = PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB, .device = PCI_DID_AMD_17H_MODEL_A0AF_NB,
}; };

View File

@ -50,7 +50,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
} }
} else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) {
if (dev->path.pci.devfn == XHCI2_DEVFN if (dev->path.pci.devfn == XHCI2_DEVFN
&& dev->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2) { && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
*gpe = xhci_sci_sources[2].gpe; *gpe = xhci_sci_sources[2].gpe;
return CB_SUCCESS; return CB_SUCCESS;
} }
@ -62,7 +62,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
static void configure_xhci_sci(void *unused) static void configure_xhci_sci(void *unused)
{ {
const struct device *xhci_2 = DEV_PTR(xhci_2); const struct device *xhci_2 = DEV_PTR(xhci_2);
if (xhci_2->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2) if (xhci_2->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2)
gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
else else
gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1); gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);

View File

@ -21,8 +21,8 @@
/* /*
* Internal Graphics * Internal Graphics
* Device IDs subject to SKU/OPN variation * Device IDs subject to SKU/OPN variation
* GFX_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX * GFX_DEVID for merlinfalcon PCI_DID_AMD_15H_MODEL_606F_GFX
* GFX_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX * GFX_DEVID for stoneyridge PCI_DID_AMD_15H_MODEL_707F_GFX
*/ */
#define GFX_DEV 0x1 #define GFX_DEV 0x1
#define GFX_FUNC 0 #define GFX_FUNC 0
@ -31,8 +31,8 @@
/* HD Audio 0 /* HD Audio 0
* Device IDs * Device IDs
* HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA * HDA0_DEVID PCI_DID_AMD_15H_MODEL_606F_HDA
* HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA * HDA0_DEVID PCI_DID_AMD_15H_MODEL_707F_HDA
*/ */
#define HDA0_DEV 0x1 #define HDA0_DEV 0x1
#define HDA0_FUNC 1 #define HDA0_FUNC 1
@ -89,8 +89,8 @@
/* HT Configuration /* HT Configuration
* Device IDs * Device IDs
* HT_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT * HT_DEVID for merlinfalcon PCI_DID_AMD_15H_MODEL_606F_NB_HT
* HT_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT * HT_DEVID for stoneyridge PCI_DID_AMD_15H_MODEL_707F_NB_HT
*/ */
#define HT_DEV 0x18 #define HT_DEV 0x18
#define HT_FUNC 0 #define HT_FUNC 0

View File

@ -320,13 +320,13 @@ static struct device_operations northbridge_operations = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, PCI_DID_AMD_15H_MODEL_606F_NB_HT,
PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, PCI_DID_AMD_15H_MODEL_707F_NB_HT,
0 }; 0 };
static const struct pci_driver family15_northbridge __pci_driver = { static const struct pci_driver family15_northbridge __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -52,17 +52,17 @@ static struct device_operations usb_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_SB900_USB_18_0, PCI_DID_AMD_SB900_USB_18_0,
PCI_DEVICE_ID_AMD_SB900_USB_18_2, PCI_DID_AMD_SB900_USB_18_2,
PCI_DEVICE_ID_AMD_SB900_USB_20_5, PCI_DID_AMD_SB900_USB_20_5,
PCI_DEVICE_ID_AMD_CZ_USB_0, PCI_DID_AMD_CZ_USB_0,
PCI_DEVICE_ID_AMD_CZ_USB_1, PCI_DID_AMD_CZ_USB_1,
PCI_DEVICE_ID_AMD_CZ_USB3_0, PCI_DID_AMD_CZ_USB3_0,
0 0
}; };
static const struct pci_driver usb_0_driver __pci_driver = { static const struct pci_driver usb_0_driver __pci_driver = {
.ops = &usb_ops, .ops = &usb_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VID_AMD,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

View File

@ -22,7 +22,7 @@ static struct device_operations device_ops = {
static const struct pci_driver soc_cavium_uart __pci_driver = { static const struct pci_driver soc_cavium_uart __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_CAVIUM, .vendor = PCI_VENDOR_CAVIUM,
.device = PCI_DEVICE_ID_CAVIUM_THUNDERX_UART, .device = PCI_DID_CAVIUM_THUNDERX_UART,
}; };
struct chip_operations soc_cavium_common_pci_ops = { struct chip_operations soc_cavium_common_pci_ops = {

View File

@ -34,21 +34,21 @@ static struct {
u16 mchid; u16 mchid;
const char *name; const char *name;
} mch_table[] = { } mch_table[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_1, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_3, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_4, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_5, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_6, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_7, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_8, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_9, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, "Alderlake-P" }, { PCI_DID_INTEL_ADL_P_ID_10, "Alderlake-P" },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DID_INTEL_ADL_M_ID_1, "Alderlake-M" },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, { PCI_DID_INTEL_ADL_M_ID_2, "Alderlake-M" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_1, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_3, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_4, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
}; };
@ -56,76 +56,76 @@ static struct {
u16 espiid; u16 espiid;
const char *name; const char *name;
} pch_table[] = { } pch_table[] = {
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, { PCI_DID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" }, { PCI_DID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" }, { PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
{ PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" }, { PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
}; };
static struct { static struct {
u16 igdid; u16 igdid;
const char *name; const char *name;
} igd_table[] = { } igd_table[] = {
{ PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" }, { PCI_DID_INTEL_ADL_GT0, "Alderlake GT0" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_1, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_2, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_3, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_4, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_5, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_6, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_7, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_8, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, { PCI_DID_INTEL_ADL_GT1_9, "Alderlake GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_2, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_2, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" }, { PCI_DID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, { PCI_DID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" }, { PCI_DID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" }, { PCI_DID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
{ PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, { PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
{ PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, { PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
{ PCI_DEVICE_ID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, { PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
}; };
static inline uint8_t get_dev_revision(pci_devfn_t dev) static inline uint8_t get_dev_revision(pci_devfn_t dev)

View File

@ -48,19 +48,19 @@ static const struct {
enum soc_intel_alderlake_power_limits limits; enum soc_intel_alderlake_power_limits limits;
enum soc_intel_alderlake_cpu_tdps cpu_tdp; enum soc_intel_alderlake_cpu_tdps cpu_tdp;
} cpuid_to_adl[] = { } cpuid_to_adl[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
}; };
/* Types of display ports */ /* Types of display ports */

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@ -174,43 +174,43 @@ void soc_init_cpus(struct bus *cpu_bus)
enum adl_cpu_type get_adl_cpu_type(void) enum adl_cpu_type get_adl_cpu_type(void)
{ {
const uint16_t adl_m_mch_ids[] = { const uint16_t adl_m_mch_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_M_ID_1, PCI_DID_INTEL_ADL_M_ID_1,
PCI_DEVICE_ID_INTEL_ADL_M_ID_2, PCI_DID_INTEL_ADL_M_ID_2,
}; };
const uint16_t adl_p_mch_ids[] = { const uint16_t adl_p_mch_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_P_ID_1, PCI_DID_INTEL_ADL_P_ID_1,
PCI_DEVICE_ID_INTEL_ADL_P_ID_3, PCI_DID_INTEL_ADL_P_ID_3,
PCI_DEVICE_ID_INTEL_ADL_P_ID_4, PCI_DID_INTEL_ADL_P_ID_4,
PCI_DEVICE_ID_INTEL_ADL_P_ID_5, PCI_DID_INTEL_ADL_P_ID_5,
PCI_DEVICE_ID_INTEL_ADL_P_ID_6, PCI_DID_INTEL_ADL_P_ID_6,
PCI_DEVICE_ID_INTEL_ADL_P_ID_7, PCI_DID_INTEL_ADL_P_ID_7,
PCI_DEVICE_ID_INTEL_ADL_P_ID_8, PCI_DID_INTEL_ADL_P_ID_8,
PCI_DEVICE_ID_INTEL_ADL_P_ID_9, PCI_DID_INTEL_ADL_P_ID_9,
PCI_DEVICE_ID_INTEL_ADL_P_ID_10 PCI_DID_INTEL_ADL_P_ID_10
}; };
const uint16_t adl_s_mch_ids[] = { const uint16_t adl_s_mch_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_S_ID_1, PCI_DID_INTEL_ADL_S_ID_1,
PCI_DEVICE_ID_INTEL_ADL_S_ID_2, PCI_DID_INTEL_ADL_S_ID_2,
PCI_DEVICE_ID_INTEL_ADL_S_ID_3, PCI_DID_INTEL_ADL_S_ID_3,
PCI_DEVICE_ID_INTEL_ADL_S_ID_4, PCI_DID_INTEL_ADL_S_ID_4,
PCI_DEVICE_ID_INTEL_ADL_S_ID_5, PCI_DID_INTEL_ADL_S_ID_5,
PCI_DEVICE_ID_INTEL_ADL_S_ID_6, PCI_DID_INTEL_ADL_S_ID_6,
PCI_DEVICE_ID_INTEL_ADL_S_ID_7, PCI_DID_INTEL_ADL_S_ID_7,
PCI_DEVICE_ID_INTEL_ADL_S_ID_8, PCI_DID_INTEL_ADL_S_ID_8,
PCI_DEVICE_ID_INTEL_ADL_S_ID_9, PCI_DID_INTEL_ADL_S_ID_9,
PCI_DEVICE_ID_INTEL_ADL_S_ID_10, PCI_DID_INTEL_ADL_S_ID_10,
PCI_DEVICE_ID_INTEL_ADL_S_ID_11, PCI_DID_INTEL_ADL_S_ID_11,
PCI_DEVICE_ID_INTEL_ADL_S_ID_12, PCI_DID_INTEL_ADL_S_ID_12,
PCI_DEVICE_ID_INTEL_ADL_S_ID_13, PCI_DID_INTEL_ADL_S_ID_13,
PCI_DEVICE_ID_INTEL_ADL_S_ID_14, PCI_DID_INTEL_ADL_S_ID_14,
PCI_DEVICE_ID_INTEL_ADL_S_ID_15, PCI_DID_INTEL_ADL_S_ID_15,
}; };
const uint16_t adl_n_mch_ids[] = { const uint16_t adl_n_mch_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_N_ID_1, PCI_DID_INTEL_ADL_N_ID_1,
PCI_DEVICE_ID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_2,
PCI_DEVICE_ID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_3,
PCI_DEVICE_ID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_4,
}; };
const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),

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@ -309,17 +309,17 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
} }
switch (mch_id) { switch (mch_id) {
case PCI_DEVICE_ID_INTEL_ADL_P_ID_1: case PCI_DID_INTEL_ADL_P_ID_1:
case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: case PCI_DID_INTEL_ADL_P_ID_3:
case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: case PCI_DID_INTEL_ADL_P_ID_5:
case PCI_DEVICE_ID_INTEL_ADL_P_ID_6: case PCI_DID_INTEL_ADL_P_ID_6:
case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: case PCI_DID_INTEL_ADL_P_ID_7:
tdp = get_cpu_tdp(); tdp = get_cpu_tdp();
if (tdp == TDP_45W) if (tdp == TDP_45W)
return ICC_MAX_TDP_45W; return ICC_MAX_TDP_45W;
return ICC_MAX_TDP_15W_28W; return ICC_MAX_TDP_15W_28W;
case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: case PCI_DID_INTEL_ADL_M_ID_1:
case PCI_DEVICE_ID_INTEL_ADL_M_ID_2: case PCI_DID_INTEL_ADL_M_ID_2:
return ICC_MAX_ID_ADL_M_MA; return ICC_MAX_ID_ADL_M_MA;
default: default:
printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",

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@ -59,55 +59,55 @@ static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, c
/* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */ /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */
static const struct vr_lookup vr_config_ll[] = { static const struct vr_lookup vr_config_ll[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
}; };
static const struct vr_lookup vr_config_icc[] = { static const struct vr_lookup vr_config_icc[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) }, { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
}; };
static const struct vr_lookup vr_config_tdc_timewindow[] = { static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
}; };
static const struct vr_lookup vr_config_tdc_currentlimit[] = { static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
}; };
void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,

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@ -28,27 +28,27 @@ static struct {
u16 mchid; u16 mchid;
const char *name; const char *name;
} mch_table[] = { } mch_table[] = {
{ PCI_DEVICE_ID_INTEL_GLK_NB, "Geminilake" }, { PCI_DID_INTEL_GLK_NB, "Geminilake" },
{ PCI_DEVICE_ID_INTEL_APL_NB, "Apollolake" }, { PCI_DID_INTEL_APL_NB, "Apollolake" },
}; };
static struct { static struct {
u16 lpcid; u16 lpcid;
const char *name; const char *name;
} pch_table[] = { } pch_table[] = {
{ PCI_DEVICE_ID_INTEL_APL_LPC, "Apollolake" }, { PCI_DID_INTEL_APL_LPC, "Apollolake" },
{ PCI_DEVICE_ID_INTEL_GLK_LPC, "Geminilake" }, { PCI_DID_INTEL_GLK_LPC, "Geminilake" },
{ PCI_DEVICE_ID_INTEL_GLK_ESPI, "Geminilake" }, { PCI_DID_INTEL_GLK_ESPI, "Geminilake" },
}; };
static struct { static struct {
u16 igdid; u16 igdid;
const char *name; const char *name;
} igd_table[] = { } igd_table[] = {
{ PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, "Apollolake HD 505" }, { PCI_DID_INTEL_APL_IGD_HD_505, "Apollolake HD 505" },
{ PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, "Apollolake HD 500" }, { PCI_DID_INTEL_APL_IGD_HD_500, "Apollolake HD 500" },
{ PCI_DEVICE_ID_INTEL_GLK_IGD, "Geminilake" }, { PCI_DID_INTEL_GLK_IGD, "Geminilake" },
{ PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, "Geminilake EU12" }, { PCI_DID_INTEL_GLK_IGD_EU12, "Geminilake EU12" },
}; };
static uint8_t get_dev_revision(pci_devfn_t dev) static uint8_t get_dev_revision(pci_devfn_t dev)

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@ -158,6 +158,6 @@ static struct device_operations ehci_device_ops = {
static const struct pci_driver baytrail_ehci __pci_driver = { static const struct pci_driver baytrail_ehci __pci_driver = {
.ops = &ehci_device_ops, .ops = &ehci_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = EHCI_DEVID .device = EHCI_DEVID
}; };

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@ -51,6 +51,6 @@ static struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = MMC45_DEVID, .device = MMC45_DEVID,
}; };

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@ -387,6 +387,6 @@ static struct device_operations gfx_device_ops = {
static const struct pci_driver gfx_driver __pci_driver = { static const struct pci_driver gfx_driver __pci_driver = {
.ops = &gfx_device_ops, .ops = &gfx_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = GFX_DEVID, .device = GFX_DEVID,
}; };

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@ -93,6 +93,6 @@ static const struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = HDA_DEVID, .device = HDA_DEVID,
}; };

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@ -162,6 +162,6 @@ static const struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = LPE_DEVID, .device = LPE_DEVID,
}; };

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@ -177,6 +177,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -137,6 +137,6 @@ static struct device_operations nc_ops = {
static const struct pci_driver nc_driver __pci_driver = { static const struct pci_driver nc_driver __pci_driver = {
.ops = &nc_ops, .ops = &nc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = SOC_DEVID, .device = SOC_DEVID,
}; };

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@ -244,6 +244,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver pcie_root_ports __pci_driver = { static const struct pci_driver pcie_root_ports __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -209,6 +209,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver baytrail_sata __pci_driver = { static const struct pci_driver baytrail_sata __pci_driver = {
.ops = &sata_ops, .ops = &sata_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -41,6 +41,6 @@ static const struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = SD_DEVID, .device = SD_DEVID,
}; };

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@ -491,7 +491,7 @@ static struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = LPC_DEVID, .device = LPC_DEVID,
}; };

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@ -238,6 +238,6 @@ static struct device_operations xhci_device_ops = {
static const struct pci_driver baytrail_xhci __pci_driver = { static const struct pci_driver baytrail_xhci __pci_driver = {
.ops = &xhci_device_ops, .ops = &xhci_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = XHCI_DEVID .device = XHCI_DEVID
}; };

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@ -39,6 +39,6 @@ static struct device_operations emmc_device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &emmc_device_ops, .ops = &emmc_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = MMC_DEVID, .device = MMC_DEVID,
}; };

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@ -77,6 +77,6 @@ static struct device_operations gfx_device_ops = {
static const struct pci_driver gfx_driver __pci_driver = { static const struct pci_driver gfx_driver __pci_driver = {
.ops = &gfx_device_ops, .ops = &gfx_device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = GFX_DEVID, .device = GFX_DEVID,
}; };

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@ -179,6 +179,6 @@ static const struct device_operations device_ops = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = LPE_DEVID, .device = LPE_DEVID,
}; };

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@ -164,6 +164,6 @@ static const unsigned short pci_device_ids[] = {
static const struct pci_driver southcluster __pci_driver = { static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops, .ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

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@ -163,6 +163,6 @@ static struct device_operations nc_ops = {
static const struct pci_driver nc_driver __pci_driver = { static const struct pci_driver nc_driver __pci_driver = {
.ops = &nc_ops, .ops = &nc_ops,
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VID_INTEL,
.device = SOC_DEVID, .device = SOC_DEVID,
}; };

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