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mb/google/hatch: Update sleep signal assertion widths 

Based on the power rail discharge times measured on hatch,
update the assertions widths that have to be programmed in SoC.

BUG=b:129328209
TEST=warm/cold reboot and S3 are working fine on hatch.

Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Rizwan Qureshi 2019-04-10 16:58:07 +05:30 committed by Subrata Banik
parent 2efee9df85
commit 43bb6554a2
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -47,6 +47,11 @@ chip soc/intel/cannonlake
# Unlock GPIO pads
register "PchUnlockGpioPads" = "1"
register "PchPmSlpS3MinAssert" = "2" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "1" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0