nb/intel/ironlake: Clean up code style (except raminit)
Reflow lines, correct coding style and align struct members, among other things. As raminit is very large, handle it on a follow-up. Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change. Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -31,8 +31,7 @@ static void ironlake_setup_bars(void)
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/* halt timer */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
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/* halt timer */
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outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2,
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DEFAULT_PMBASE | 0x60 | 0x06);
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outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
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printk(BIOS_DEBUG, " done.\n");
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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@ -56,7 +55,7 @@ static void ironlake_setup_bars(void)
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printk(BIOS_DEBUG, " done.\n");
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}
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static void early_cpu_init (void)
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static void early_cpu_init(void)
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{
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msr_t m;
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@ -121,8 +120,7 @@ void ironlake_early_initialization(int chipset_type)
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elog_boot_notify(s3_resume);
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/* Device Enable */
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,
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DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
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early_cpu_init();
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@ -132,7 +130,7 @@ void ironlake_early_initialization(int chipset_type)
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/* Magic for S3 resume. Must be done early. */
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if (s3_resume) {
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MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
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MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
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MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
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MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
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}
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}
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@ -152,8 +152,7 @@ static void gma_func0_init(struct device *dev)
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gma_gfxinit(&lightup_ok);
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/* Linux relies on VBT for panel info. */
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generate_fake_intel_oprom(&conf->gfx, dev,
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"$VBT IRONLAKE-MOBILE");
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generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
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} else {
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/* PCI Init, will run VBIOS */
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pci_dev_init(dev);
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@ -208,7 +207,7 @@ static const unsigned short pci_device_ids[] = {
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};
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static const struct pci_driver gma __pci_driver = {
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.ops = &gma_func0_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.ops = &gma_func0_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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@ -19,16 +19,15 @@ static int bridge_revision_id = -1;
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int bridge_silicon_revision(void)
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{
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if (bridge_revision_id < 0) {
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uint8_t stepping = cpuid_eax(1) & 0xf;
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uint8_t bridge_id =
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pci_read_config16(pcidev_on_root(0, 0),
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PCI_DEVICE_ID) & 0xf0;
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bridge_revision_id = bridge_id | stepping;
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uint8_t stepping = cpuid_eax(1) & 0x0f;
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uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
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bridge_revision_id = (bridge_id & 0xf0) | stepping;
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}
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return bridge_revision_id;
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}
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/* Reserve everything between A segment and 1MB:
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/*
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* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
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@ -52,13 +51,12 @@ static void add_fixed_resources(struct device *dev, int index)
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resource = new_resource(dev, index++);
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resource->base = (resource_t) 0xfed00000;
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resource->size = (resource_t) 0x00100000;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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mmio_resource(dev, index++, legacy_hole_base_k,
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(0xc0000 >> 10) - legacy_hole_base_k);
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reserved_ram_resource(dev, index++, 0xc0000 >> 10,
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(0x100000 - 0xc0000) >> 10);
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mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
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reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
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#if CONFIG(CHROMEOS_RAMOOPS)
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reserved_ram_resource(dev, index++,
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@ -86,11 +84,11 @@ static const char *northbridge_acpi_name(const struct device *dev)
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#endif
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = northbridge_acpi_name,
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.acpi_name = northbridge_acpi_name,
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#endif
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};
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@ -191,18 +189,18 @@ static void ironlake_init(void *const chip_info)
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}
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static struct device_operations mc_ops = {
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.read_resources = mc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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.ops_pci = &pci_dev_ops_pci,
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.read_resources = mc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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.ops_pci = &pci_dev_ops_pci,
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};
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static const struct pci_driver mc_driver_ard __pci_driver = {
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x0044, /* Arrandale DRAM controller */
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x0044, /* Arrandale DRAM controller */
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};
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static struct device_operations cpu_bus_ops = {
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@ -17,7 +17,8 @@
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#include <southbridge/intel/ibexpeak/pch.h>
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#include <southbridge/intel/ibexpeak/me.h>
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/* Platform has no romstage entry point under mainboard directory,
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/*
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* Platform has no romstage entry point under mainboard directory,
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* so this one is named with prefix mainboard.
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*/
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void mainboard_romstage_entry(void)
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@ -59,7 +60,8 @@ void mainboard_romstage_entry(void)
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intel_early_me_status();
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if (s3resume) {
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/* Clear SLP_TYPE. This will break stage2 but
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/*
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* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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reg32 = inl(DEFAULT_PMBASE + 0x04);
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