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nb/intel/ironlake: Clean up code style (except raminit) 

Reflow lines, correct coding style and align struct members, among
other things. As raminit is very large, handle it on a follow-up.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change.

Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-22 18:11:31 +02:00
parent aee3b148ba
commit 43bcc7b6ed
4 changed files with 35 additions and 38 deletions
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6
src/northbridge/intel/ironlake/early_init.c
View File

@ -31,8 +31,7 @@ static void ironlake_setup_bars(void)
/* halt timer */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
/* halt timer */
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2,
DEFAULT_PMBASE | 0x60 | 0x06);
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
@ -121,8 +120,7 @@ void ironlake_early_initialization(int chipset_type)
elog_boot_notify(s3_resume);
/* Device Enable */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,
DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST);
early_cpu_init();

3
src/northbridge/intel/ironlake/gma.c
View File

@ -152,8 +152,7 @@ static void gma_func0_init(struct device *dev)
gma_gfxinit(&lightup_ok);
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
"$VBT IRONLAKE-MOBILE");
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
} else {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);

22
src/northbridge/intel/ironlake/northbridge.c
View File

@ -19,16 +19,15 @@ static int bridge_revision_id = -1;
int bridge_silicon_revision(void)
{
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id =
pci_read_config16(pcidev_on_root(0, 0),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
uint8_t stepping = cpuid_eax(1) & 0x0f;
uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
bridge_revision_id = (bridge_id & 0xf0) | stepping;
}
return bridge_revision_id;
}
/* Reserve everything between A segment and 1MB:
/*
* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
@ -52,13 +51,12 @@ static void add_fixed_resources(struct device *dev, int index)
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
resource->size = (resource_t) 0x00100000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
#if CONFIG(CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,

6
src/northbridge/intel/ironlake/romstage.c
View File

@ -17,7 +17,8 @@
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/ibexpeak/me.h>
/* Platform has no romstage entry point under mainboard directory,
/*
* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
*/
void mainboard_romstage_entry(void)
@ -59,7 +60,8 @@ void mainboard_romstage_entry(void)
intel_early_me_status();
if (s3resume) {
/* Clear SLP_TYPE. This will break stage2 but
/*
* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
reg32 = inl(DEFAULT_PMBASE + 0x04);