GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

more fixes. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-08-30 16:08:30 +00:00
parent 009f87a30b
commit 43dd85e7ec
1 changed files with 107 additions and 205 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

312
src/northbridge/intel/i855pm/raminit.c
View File

@ -145,109 +145,25 @@ static void ENABLE_REFRESH(const struct mem_controller *ctrl)
* Table: constant_register_values * Table: constant_register_values
*/ */
static const long register_values[] = { static const long register_values[] = {
/* SVID - Subsystem Vendor Identification Register
* 0x2c - 0x2d
* [15:00] Subsytem Vendor ID (Indicates system board vendor)
*/
/* SID - Subsystem Identification Register
* 0x2e - 0x2f
* [15:00] Subsystem ID
*/
0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
/* Undocumented
* 0x80 - 0x80
* This register has something to do with CAS latencies,
* possibily this is the real chipset control.
* At 0x00 CAS latency 1.5 works.
* At 0x06 CAS latency 2.5 works.
* At 0x01 CAS latency 2.0 works.
*/
/* This is still undocumented in e7501, but with different values
* CAS 2.0 values taken from Intel BIOS settings, others are a guess
* and may be terribly wrong. Old values preserved as comments until I
* figure this out for sure.
* e7501 docs claim that CAS1.5 is unsupported, so it may or may not
* work at all.
* Steven James 02/06/2003
*/
#if CAS_LATENCY == CAS_2_5
// 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
0x80, 0xfffff000, 0x0662, /* from Factory Bios */
#elif CAS_LATENCY == CAS_2_0
// 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
0x80, 0xfffff000, 0x0bb1, /* values for register 0x80 */
#endif
/* Enable periodic memory recalibration */
0x88, 0xffffff00, 0x80,
/* FDHC - Fixed DRAM Hole Control
* 0x58
* [7:7] Hole_Enable
* 0 == No memory Hole
* 1 == Memory Hole from 15MB to 16MB
* [6:0] Reserved
*
* PAM - Programmable Attribute Map
* 0x59 [1:0] Reserved
* 0x59 [5:4] 0xF0000 - 0xFFFFF
* 0x5A [1:0] 0xC0000 - 0xC3FFF
* 0x5A [5:4] 0xC4000 - 0xC7FFF
* 0x5B [1:0] 0xC8000 - 0xCBFFF
* 0x5B [5:4] 0xCC000 - 0xCFFFF
* 0x5C [1:0] 0xD0000 - 0xD3FFF
* 0x5C [5:4] 0xD4000 - 0xD7FFF
* 0x5D [1:0] 0xD8000 - 0xDBFFF
* 0x5D [5:4] 0xDC000 - 0xDFFFF
* 0x5E [1:0] 0xE0000 - 0xE3FFF
* 0x5E [5:4] 0xE4000 - 0xE7FFF
* 0x5F [1:0] 0xE8000 - 0xEBFFF
* 0x5F [5:4] 0xEC000 - 0xEFFFF
* 00 == DRAM Disabled (All Access go to memory mapped I/O space)
* 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
* 11 == Normal (All Access go to DRAM)
*/
0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
/* DRB - DRAM Row Boundary Registers /* DRB - DRAM Row Boundary Registers
* 0x60 - 0x6F * 0x60 - 0x63
* An array of 8 byte registers, which hold the ending * An array of 8 byte registers, which hold the ending
* memory address assigned to each pair of DIMMS, in 64MB * memory address assigned to each pair of DIMMS, in 32MB
* granularity. * granularity.
*/ */
/* Conservatively say each row has 64MB of ram, we will fix this up later */ /* Conservatively say each row has 32MB of ram, we will fix this up later */
0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
0x68, 0xffffffff, 0,
0x6C, 0xffffffff, 0,
/* DRA - DRAM Row Attribute Register /* DRA - DRAM Row Attribute Register
* 0x70 Row 0,1 * 0x70 Row 0,1
* 0x71 Row 2,3 * 0x71 Row 2,3
* 0x72 Row 4,5 * [2:0] Row Attributes for both rows
* 0x73 Row 6,7 * 001 == 2KB
* [7:7] Device width for Odd numbered rows * 010 == 4KB
* 0 == 8 bits wide x8 * 011 == 8KB
* 1 == 4 bits wide x4 * 100 == 16KB
* [6:4] Row Attributes for Odd numbered rows
* 010 == 8KB
* 011 == 16KB
* 100 == 32KB
* 101 == 64KB
* Others == Reserved
* [3:3] Device width for Even numbered rows
* 0 == 8 bits wide x8
* 1 == 4 bits wide x4
* [2:0] Row Attributes for Even numbered rows
* 010 == 8KB
* 011 == 16KB
* 100 == 32KB
* 101 == 64KB (This page size appears broken)
* Others == Reserved * Others == Reserved
*/ */
/* leave it alone for now -- seems bad to set it at all
0x70, 0x00000000, 0x70, 0x00000000,
(((0<<3)|(0<<0))<< 0) | (((0<<3)|(0<<0))<< 0) |
(((0<<3)|(0<<0))<< 4) | (((0<<3)|(0<<0))<< 4) |
@ -257,31 +173,45 @@ static const long register_values[] = {
(((0<<3)|(0<<0))<<20) | (((0<<3)|(0<<0))<<20) |
(((0<<3)|(0<<0))<<24) | (((0<<3)|(0<<0))<<24) |
(((0<<3)|(0<<0))<<28), (((0<<3)|(0<<0))<<28),
0x74, 0xffffffff, 0, */
/* DRT - DRAM Time Register /* DRT - DRAM Time Register
* 0x78 * 0x78
* [31:30] Reserved * [31:31] Additional CKE to CS Clock for Read/Write
* [30:30] Additional CKE to CS clock for Precharge/Activate
* [29:29] Back to Back Write-Read Turn Around * [29:29] Back to Back Write-Read Turn Around
* 0 == 3 clocks between WR-RD commands * Intel recommends set to 1
* 1 == 2 clocks between WR-RD commands *
* [28:28] Back to Back Read-Write Turn Around * [28:28] Back to Back Read-Write Turn Around
* 0 == 5 clocks between RD-WR commands * Intel recommends 0 for CL 2.5 and 1 for CL 2
* 1 == 4 clocks between RD-WR commands *
* [27:27] Back to Back Read Turn Around * [27:27] Back to Back Read Turn Around
* 0 == 4 clocks between RD commands * Intel recommends 1 for all configs
* 1 == 3 clocks between RD commands *
* [26:24] Read Delay (tRD) * [26:24] Read Delay (tRD)
* 000 == 7 clocks * 000 == 9 clocks
* 001 == 6 clocks * 001 == 8 clocks
* 010 == 5 clocks * 010 == 7 clocks
* 011 == 6 clocks
* 100 == 5 clocks
* 101 == 4 clocks
* 110 == 3 clocks
* Others == Reserved * Others == Reserved
* [23:19] Reserved * [23:20] Reserved
* [18:16] DRAM idle timer * [19:19] No Wake for DDR page closes
* 0 is default
* [18:16] Page Close Counter
* 000 == infinite * 000 == infinite
* 011 == 16 dram clocks * 010 == 8-15 clocks
* 001 == Datasheet says reserved, but Intel BIOS sets it * 011 == 16-31 clocks
* [15:11] Reserved * 100 == 64-127 clocks
* 101 == 128-255 clocks
* 110 == 192-383 clocks
* 111 == 255-510 clocks
*
* [15:12] Reserved
* [11:11] DQS Slave DLL Dynamic Management
* power saving, when set to 1, slave DLLS disabled
* we'll leave it at 0 for now
* [10:09] Active to Precharge (tRAS) * [10:09] Active to Precharge (tRAS)
* 00 == 7 clocks * 00 == 7 clocks
* 01 == 6 clocks * 01 == 6 clocks
@ -290,21 +220,19 @@ static const long register_values[] = {
* [08:06] Reserved * [08:06] Reserved
* [05:04] Cas Latency (tCL) * [05:04] Cas Latency (tCL)
* 00 == 2.5 Clocks * 00 == 2.5 Clocks
* 01 == 2.0 Clocks * 01 == 2.0 Clocks (default)
* 10 == 1.5 Clocks * 10 == 1.5 Clocks
* 11 == Reserved * 11 == Reserved
* [03:03] Write Ras# to Cas# Delay (tRCD) * [03:03] Reserved
* [02:02] Ras# to Cas# Delay (tRCD)
* 0 == 3 DRAM Clocks * 0 == 3 DRAM Clocks
* 1 == 2 DRAM Clocks * 1 == 2 DRAM Clocks
* [02:01] Read RAS# to CAS# Delay (tRCD) * [01:01] Reserved
* 00 == reserved
* 01 == reserved
* 10 == 3 DRAM Clocks
* 11 == 2 DRAM Clocks
* [00:00] DRAM RAS# to Precharge (tRP) * [00:00] DRAM RAS# to Precharge (tRP)
* 0 == 3 DRAM Clocks * 0 == 3 DRAM Clocks
* 1 == 2 DRAM Clocks * 1 == 2 DRAM Clocks
*/ */
#define DRT_CAS_2_5 (0<<4) #define DRT_CAS_2_5 (0<<4)
#define DRT_CAS_2_0 (1<<4) #define DRT_CAS_2_0 (1<<4)
#define DRT_CAS_1_5 (2<<4) #define DRT_CAS_1_5 (2<<4)
@ -318,42 +246,79 @@ static const long register_values[] = {
#define DRT_CL DRT_CAS_1_5 #define DRT_CL DRT_CAS_1_5
#endif #endif
/* Most aggressive settings possible */ /* Most unaggressive settings possible */
/* clear bits 26:24,18:16,11,10:9,5:4,2:2,0 */
/* ~ (7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1 */
// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0), // 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0),
// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0), // 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0), // 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
0x78, ~((7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1),
(1<<29)|(1<<28)|(9<<26)|(0<<18)|(0<<11)|(0<<10)|(0<<5)|(0<<2)|(0<<0),
/* FDHC - Fixed DRAM Hole Control
* 0x97
* [7:7] Hole_Enable
* 0 == No memory Hole
* 1 == Memory Hole from 15MB to 16MB
* [6:0] Reserved
*
* PAM - Programmable Attribute Map
* 0x90 [3:0] Reserved
* 0x90 [5:4] 0xF0000 - 0xFFFFF
* 0x91 [1:0] 0xC0000 - 0xC3FFF
* 0x91 [5:4] 0xC4000 - 0xC7FFF
* 0x92 [1:0] 0xC8000 - 0xCBFFF
* 0x92 [5:4] 0xCC000 - 0xCFFFF
* 0x93 [1:0] 0xD0000 - 0xD3FFF
* 0x93 [5:4] 0xD4000 - 0xD7FFF
* 0x94 [1:0] 0xD8000 - 0xDBFFF
* 0x94 [5:4] 0xDC000 - 0xDFFFF
* 0x95 [1:0] 0xE0000 - 0xE3FFF
* 0x95 [5:4] 0xE4000 - 0xE7FFF
* 0x96 [1:0] 0xE8000 - 0xEBFFF
* 0x96 [5:4] 0xEC000 - 0xEFFFF
* 00 == DRAM Disabled (All Access go to memory mapped I/O space)
* 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
* 11 == Normal (All Access go to DRAM)
*/
0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
/* FIXME why was I attempting to set a reserved bit? */ /* FIXME why was I attempting to set a reserved bit? */
/* 0x0100040f */ /* 0x0100040f */
/* DRC - DRAM Contoller Mode Register /* DRC - DRAM Contoller Mode Register
* 0x7c * 0x7c
* [31:30] Reserved * [31:30] Rev #
* [29:29] Initialization Complete * [29:29] Initialization Complete
* 0 == Not Complete * 0 == Not Complete
* 1 == Complete * 1 == Complete
* [28:23] Reserved * [28:27] Dynamic Power Down Enable (leave at 0 for now)
* [22:22] Channels * [27:24] Reserved
* 0 == Single channel * [23:23] Reduced Comamnd Drive Delay (leave at 0 for now)
* 1 == Dual Channel * [22:22] Reduced Command Drive Enable (leave at 0 for now)
* [21:20] DRAM Data Integrity Mode * [21:21] DRAM Data Integrity Mode
* 00 == Disabled, no ECC * 0 == Disabled, no ECC
* 01 == Reserved * 1 == Error checking, with correction
* 10 == Error checking, using chip-kill, with correction * [20:20] Reserved
* 11 == Reserved
* [19:18] Reserved * [19:18] Reserved
* Must equal 01 * Must equal 00
* [17:17] (Intel Undocumented) should always be set to 1 * [17:17] (Intel Undocumented) should always be set to
* [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) * [16:16] Disable SCK Tri-state in C3/S1-m
* 0 == 2n Rule * 0 == 2n Rule
* 1 == 1n rule * 1 == 1n rule
* [15:11] Reserved * [15:14] Reserved
* [13:13] Dynamic CS Disable
* [12:12] SM Interface Tristate enable
* [11:11] Reserved
* [10:08] Refresh mode select * [10:08] Refresh mode select
* 000 == Refresh disabled * 000 == Refresh disabled
* 001 == Refresh interval 15.6 usec * 001 == Refresh interval 15.6 usec
* 010 == Refresh interval 7.8 usec * 010 == Refresh interval 7.8 usec
* 011 == Refresh interval 64 usec * 011 == Refresh interval 64 usec
* 111 == Refresh every 64 clocks (fast refresh) * 111 == Reserved
* [07:07] Reserved * [07:07] Reserved
* [06:04] Mode Select (SMS) * [06:04] Mode Select (SMS)
* 000 == Self Refresh Mode * 000 == Self Refresh Mode
@ -364,78 +329,15 @@ static const long register_values[] = {
* 101 == Reserved * 101 == Reserved
* 110 == CBR Refresh * 110 == CBR Refresh
* 111 == Normal Operation * 111 == Normal Operation
* [03:00] Reserved * [03:01] Reserved
* [00:00] DRAM type --hardwired to 1 to indicate DDR
*/ */
// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), // .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8), // 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
0x7c, 0xff82f8ff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
/* Another Intel undocumented register */
0x88, 0x080007ff, (1<<31)|(1 << 30)|(1<<28)|(0 << 26)|(0x10 << 21)|(10 << 16)|(0x13 << 11),
/* CLOCK_DIS - CK/CK# Disable Register
* 0x8C
* [7:4] Reserved
* [3:3] CK3
* 0 == Enable
* 1 == Disable
* [2:2] CK2
* 0 == Enable
* 1 == Disable
* [1:1] CK1
* 0 == Enable
* 1 == Disable
* [0:0] CK0
* 0 == Enable
* 1 == Disable
*/
0x8C, 0xfffffff0, 0xf,
/* TOLM - Top of Low Memory Register
* 0xC4 - 0xC5
* [15:11] Top of low memory (TOLM)
* The address below 4GB that should be treated as RAM,
* on a 128MB granularity.
* [10:00] Reserved
*/
/* REMAPBASE - Remap Base Address Regsiter
* 0xC6 - 0xC7
* [15:10] Reserved
* [09:00] Remap Base Address [35:26] 64M aligned
* Bits [25:0] are assumed to be 0.
*/
0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
/* REMAPLIMIT - Remap Limit Address Register
* 0xC8 - 0xC9
* [15:10] Reserved
* [09:00] Remap Limit Address [35:26] 64M aligned
* When remaplimit < remapbase this register is disabled.
*/
0xc8, 0xfffffc00, 0,
/* DVNP - Device Not Present Register
* 0xE0 - 0xE1
* [15:05] Reserved
* [04:04] Device 4 Function 1 Present
* 0 == Present
* 1 == Absent
* [03:03] Device 3 Function 1 Present
* 0 == Present
* 1 == Absent
* [02:02] Device 2 Function 1 Present
* 0 == Present
* 1 == Absent
* [01:01] Reserved
* [00:00] Device 0 Function 1 Present
* 0 == Present
* 1 == Absent
*/
0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
0xd8, 0xffff9fff, 0x00000000,
0xf4, 0x3f8ffffd, 0x40300002,
0x1050, 0xffffffcf, 0x00000030,
}; };
@ -494,9 +396,9 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
#endif #endif
/*enable access to the rcomp bar */ /*enable access to the rcomp bar */
/* for e7501 they also set bit 31 ... */
dword = pci_read_config32(ctrl->d0, 0x0f4); dword = pci_read_config32(ctrl->d0, 0x0f4);
dword &= ~(1<<31); dword |= 1<<22;
dword |=((1<<30)|1<<22);
pci_write_config32(ctrl->d0, 0x0f4, dword); pci_write_config32(ctrl->d0, 0x0f4, dword);
@ -507,7 +409,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
dword |= (1<<9); dword |= (1<<9);
write32(RCOMP_MMIO + 0x20, dword); write32(RCOMP_MMIO + 0x20, dword);
#ifdef NOTNOW
/* Begin to write the RCOMP registers */ /* Begin to write the RCOMP registers */
write8(RCOMP_MMIO + 0x2c, 0xff); write8(RCOMP_MMIO + 0x2c, 0xff);
@ -564,7 +466,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
/* Wait 40 usec */ /* Wait 40 usec */
SLOW_DOWN_IO; SLOW_DOWN_IO;
#endif
/*disable access to the rcomp bar */ /*disable access to the rcomp bar */
dword = pci_read_config32(ctrl->d0, 0x0f4); dword = pci_read_config32(ctrl->d0, 0x0f4);
dword &= ~(1<<22); dword &= ~(1<<22);