more fixes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
009f87a30b
commit
43dd85e7ec
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@ -145,109 +145,25 @@ static void ENABLE_REFRESH(const struct mem_controller *ctrl)
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* Table: constant_register_values
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*/
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static const long register_values[] = {
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/* SVID - Subsystem Vendor Identification Register
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* 0x2c - 0x2d
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* [15:00] Subsytem Vendor ID (Indicates system board vendor)
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*/
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/* SID - Subsystem Identification Register
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* 0x2e - 0x2f
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* [15:00] Subsystem ID
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*/
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0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
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/* Undocumented
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* 0x80 - 0x80
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* This register has something to do with CAS latencies,
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* possibily this is the real chipset control.
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* At 0x00 CAS latency 1.5 works.
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* At 0x06 CAS latency 2.5 works.
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* At 0x01 CAS latency 2.0 works.
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*/
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/* This is still undocumented in e7501, but with different values
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* CAS 2.0 values taken from Intel BIOS settings, others are a guess
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* and may be terribly wrong. Old values preserved as comments until I
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* figure this out for sure.
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* e7501 docs claim that CAS1.5 is unsupported, so it may or may not
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* work at all.
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* Steven James 02/06/2003
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*/
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#if CAS_LATENCY == CAS_2_5
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// 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
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0x80, 0xfffff000, 0x0662, /* from Factory Bios */
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#elif CAS_LATENCY == CAS_2_0
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// 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
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0x80, 0xfffff000, 0x0bb1, /* values for register 0x80 */
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#endif
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/* Enable periodic memory recalibration */
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0x88, 0xffffff00, 0x80,
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/* FDHC - Fixed DRAM Hole Control
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* 0x58
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* [7:7] Hole_Enable
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* 0 == No memory Hole
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* 1 == Memory Hole from 15MB to 16MB
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* [6:0] Reserved
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*
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* PAM - Programmable Attribute Map
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* 0x59 [1:0] Reserved
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* 0x59 [5:4] 0xF0000 - 0xFFFFF
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* 0x5A [1:0] 0xC0000 - 0xC3FFF
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* 0x5A [5:4] 0xC4000 - 0xC7FFF
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* 0x5B [1:0] 0xC8000 - 0xCBFFF
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* 0x5B [5:4] 0xCC000 - 0xCFFFF
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* 0x5C [1:0] 0xD0000 - 0xD3FFF
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* 0x5C [5:4] 0xD4000 - 0xD7FFF
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* 0x5D [1:0] 0xD8000 - 0xDBFFF
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* 0x5D [5:4] 0xDC000 - 0xDFFFF
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* 0x5E [1:0] 0xE0000 - 0xE3FFF
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* 0x5E [5:4] 0xE4000 - 0xE7FFF
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* 0x5F [1:0] 0xE8000 - 0xEBFFF
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* 0x5F [5:4] 0xEC000 - 0xEFFFF
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* 00 == DRAM Disabled (All Access go to memory mapped I/O space)
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* 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
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* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
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* 11 == Normal (All Access go to DRAM)
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*/
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0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
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0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
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/* DRB - DRAM Row Boundary Registers
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* 0x60 - 0x6F
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* 0x60 - 0x63
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* An array of 8 byte registers, which hold the ending
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* memory address assigned to each pair of DIMMS, in 64MB
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* memory address assigned to each pair of DIMMS, in 32MB
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* granularity.
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*/
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/* Conservatively say each row has 64MB of ram, we will fix this up later */
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/* Conservatively say each row has 32MB of ram, we will fix this up later */
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0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
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0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
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0x68, 0xffffffff, 0,
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0x6C, 0xffffffff, 0,
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/* DRA - DRAM Row Attribute Register
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* 0x70 Row 0,1
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* 0x71 Row 2,3
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* 0x72 Row 4,5
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* 0x73 Row 6,7
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* [7:7] Device width for Odd numbered rows
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* 0 == 8 bits wide x8
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* 1 == 4 bits wide x4
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* [6:4] Row Attributes for Odd numbered rows
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* 010 == 8KB
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* 011 == 16KB
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* 100 == 32KB
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* 101 == 64KB
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* Others == Reserved
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* [3:3] Device width for Even numbered rows
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* 0 == 8 bits wide x8
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* 1 == 4 bits wide x4
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* [2:0] Row Attributes for Even numbered rows
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* 010 == 8KB
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* 011 == 16KB
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* 100 == 32KB
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* 101 == 64KB (This page size appears broken)
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* [2:0] Row Attributes for both rows
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* 001 == 2KB
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* 010 == 4KB
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* 011 == 8KB
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* 100 == 16KB
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* Others == Reserved
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*/
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/* leave it alone for now -- seems bad to set it at all
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0x70, 0x00000000,
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(((0<<3)|(0<<0))<< 0) |
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(((0<<3)|(0<<0))<< 4) |
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@ -257,31 +173,45 @@ static const long register_values[] = {
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(((0<<3)|(0<<0))<<20) |
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(((0<<3)|(0<<0))<<24) |
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(((0<<3)|(0<<0))<<28),
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0x74, 0xffffffff, 0,
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*/
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/* DRT - DRAM Time Register
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* 0x78
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* [31:30] Reserved
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* [31:31] Additional CKE to CS Clock for Read/Write
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* [30:30] Additional CKE to CS clock for Precharge/Activate
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* [29:29] Back to Back Write-Read Turn Around
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* 0 == 3 clocks between WR-RD commands
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* 1 == 2 clocks between WR-RD commands
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* Intel recommends set to 1
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*
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* [28:28] Back to Back Read-Write Turn Around
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* 0 == 5 clocks between RD-WR commands
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* 1 == 4 clocks between RD-WR commands
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* Intel recommends 0 for CL 2.5 and 1 for CL 2
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*
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* [27:27] Back to Back Read Turn Around
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* 0 == 4 clocks between RD commands
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* 1 == 3 clocks between RD commands
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* Intel recommends 1 for all configs
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*
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* [26:24] Read Delay (tRD)
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* 000 == 7 clocks
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* 001 == 6 clocks
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* 010 == 5 clocks
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* 000 == 9 clocks
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* 001 == 8 clocks
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* 010 == 7 clocks
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* 011 == 6 clocks
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* 100 == 5 clocks
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* 101 == 4 clocks
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* 110 == 3 clocks
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* Others == Reserved
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* [23:19] Reserved
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* [18:16] DRAM idle timer
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* [23:20] Reserved
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* [19:19] No Wake for DDR page closes
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* 0 is default
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* [18:16] Page Close Counter
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* 000 == infinite
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* 011 == 16 dram clocks
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* 001 == Datasheet says reserved, but Intel BIOS sets it
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* [15:11] Reserved
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* 010 == 8-15 clocks
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* 011 == 16-31 clocks
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* 100 == 64-127 clocks
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* 101 == 128-255 clocks
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* 110 == 192-383 clocks
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* 111 == 255-510 clocks
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*
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* [15:12] Reserved
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* [11:11] DQS Slave DLL Dynamic Management
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* power saving, when set to 1, slave DLLS disabled
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* we'll leave it at 0 for now
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* [10:09] Active to Precharge (tRAS)
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* 00 == 7 clocks
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* 01 == 6 clocks
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@ -290,21 +220,19 @@ static const long register_values[] = {
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* [08:06] Reserved
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* [05:04] Cas Latency (tCL)
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* 00 == 2.5 Clocks
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* 01 == 2.0 Clocks
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* 01 == 2.0 Clocks (default)
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* 10 == 1.5 Clocks
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* 11 == Reserved
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* [03:03] Write Ras# to Cas# Delay (tRCD)
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* [03:03] Reserved
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* [02:02] Ras# to Cas# Delay (tRCD)
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* 0 == 3 DRAM Clocks
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* 1 == 2 DRAM Clocks
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* [02:01] Read RAS# to CAS# Delay (tRCD)
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* 00 == reserved
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* 01 == reserved
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* 10 == 3 DRAM Clocks
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* 11 == 2 DRAM Clocks
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* [01:01] Reserved
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* [00:00] DRAM RAS# to Precharge (tRP)
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* 0 == 3 DRAM Clocks
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* 1 == 2 DRAM Clocks
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*/
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#define DRT_CAS_2_5 (0<<4)
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#define DRT_CAS_2_0 (1<<4)
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#define DRT_CAS_1_5 (2<<4)
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@ -318,42 +246,79 @@ static const long register_values[] = {
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#define DRT_CL DRT_CAS_1_5
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#endif
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/* Most aggressive settings possible */
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/* Most unaggressive settings possible */
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/* clear bits 26:24,18:16,11,10:9,5:4,2:2,0 */
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/* ~ (7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1 */
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// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0),
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// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
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0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
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// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
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0x78, ~((7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1),
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(1<<29)|(1<<28)|(9<<26)|(0<<18)|(0<<11)|(0<<10)|(0<<5)|(0<<2)|(0<<0),
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/* FDHC - Fixed DRAM Hole Control
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* 0x97
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* [7:7] Hole_Enable
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* 0 == No memory Hole
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* 1 == Memory Hole from 15MB to 16MB
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* [6:0] Reserved
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*
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* PAM - Programmable Attribute Map
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* 0x90 [3:0] Reserved
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* 0x90 [5:4] 0xF0000 - 0xFFFFF
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* 0x91 [1:0] 0xC0000 - 0xC3FFF
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* 0x91 [5:4] 0xC4000 - 0xC7FFF
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* 0x92 [1:0] 0xC8000 - 0xCBFFF
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* 0x92 [5:4] 0xCC000 - 0xCFFFF
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* 0x93 [1:0] 0xD0000 - 0xD3FFF
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* 0x93 [5:4] 0xD4000 - 0xD7FFF
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* 0x94 [1:0] 0xD8000 - 0xDBFFF
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* 0x94 [5:4] 0xDC000 - 0xDFFFF
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* 0x95 [1:0] 0xE0000 - 0xE3FFF
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* 0x95 [5:4] 0xE4000 - 0xE7FFF
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* 0x96 [1:0] 0xE8000 - 0xEBFFF
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* 0x96 [5:4] 0xEC000 - 0xEFFFF
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* 00 == DRAM Disabled (All Access go to memory mapped I/O space)
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* 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
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* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
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* 11 == Normal (All Access go to DRAM)
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*/
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0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
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0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
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/* FIXME why was I attempting to set a reserved bit? */
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/* 0x0100040f */
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/* DRC - DRAM Contoller Mode Register
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* 0x7c
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* [31:30] Reserved
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* [31:30] Rev #
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* [29:29] Initialization Complete
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* 0 == Not Complete
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* 1 == Complete
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* [28:23] Reserved
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* [22:22] Channels
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* 0 == Single channel
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* 1 == Dual Channel
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* [21:20] DRAM Data Integrity Mode
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* 00 == Disabled, no ECC
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* 01 == Reserved
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* 10 == Error checking, using chip-kill, with correction
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* 11 == Reserved
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* [28:27] Dynamic Power Down Enable (leave at 0 for now)
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* [27:24] Reserved
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* [23:23] Reduced Comamnd Drive Delay (leave at 0 for now)
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* [22:22] Reduced Command Drive Enable (leave at 0 for now)
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* [21:21] DRAM Data Integrity Mode
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* 0 == Disabled, no ECC
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* 1 == Error checking, with correction
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* [20:20] Reserved
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* [19:18] Reserved
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* Must equal 01
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* [17:17] (Intel Undocumented) should always be set to 1
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* [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
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* Must equal 00
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* [17:17] (Intel Undocumented) should always be set to
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* [16:16] Disable SCK Tri-state in C3/S1-m
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* 0 == 2n Rule
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* 1 == 1n rule
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* [15:11] Reserved
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* [15:14] Reserved
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* [13:13] Dynamic CS Disable
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* [12:12] SM Interface Tristate enable
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* [11:11] Reserved
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* [10:08] Refresh mode select
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* 000 == Refresh disabled
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* 001 == Refresh interval 15.6 usec
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* 010 == Refresh interval 7.8 usec
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* 011 == Refresh interval 64 usec
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* 111 == Refresh every 64 clocks (fast refresh)
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* 111 == Reserved
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* [07:07] Reserved
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* [06:04] Mode Select (SMS)
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* 000 == Self Refresh Mode
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@ -364,78 +329,15 @@ static const long register_values[] = {
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* 101 == Reserved
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* 110 == CBR Refresh
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* 111 == Normal Operation
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* [03:00] Reserved
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* [03:01] Reserved
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* [00:00] DRAM type --hardwired to 1 to indicate DDR
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*/
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// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
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// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
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// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
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0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
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// 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
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0x7c, 0xff82f8ff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
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/* Another Intel undocumented register */
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0x88, 0x080007ff, (1<<31)|(1 << 30)|(1<<28)|(0 << 26)|(0x10 << 21)|(10 << 16)|(0x13 << 11),
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/* CLOCK_DIS - CK/CK# Disable Register
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* 0x8C
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* [7:4] Reserved
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* [3:3] CK3
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* 0 == Enable
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* 1 == Disable
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* [2:2] CK2
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* 0 == Enable
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* 1 == Disable
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* [1:1] CK1
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* 0 == Enable
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* 1 == Disable
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* [0:0] CK0
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* 0 == Enable
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* 1 == Disable
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*/
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0x8C, 0xfffffff0, 0xf,
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/* TOLM - Top of Low Memory Register
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* 0xC4 - 0xC5
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* [15:11] Top of low memory (TOLM)
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* The address below 4GB that should be treated as RAM,
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* on a 128MB granularity.
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* [10:00] Reserved
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*/
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/* REMAPBASE - Remap Base Address Regsiter
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* 0xC6 - 0xC7
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* [15:10] Reserved
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* [09:00] Remap Base Address [35:26] 64M aligned
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* Bits [25:0] are assumed to be 0.
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*/
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0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
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/* REMAPLIMIT - Remap Limit Address Register
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* 0xC8 - 0xC9
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* [15:10] Reserved
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* [09:00] Remap Limit Address [35:26] 64M aligned
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* When remaplimit < remapbase this register is disabled.
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*/
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0xc8, 0xfffffc00, 0,
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/* DVNP - Device Not Present Register
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* 0xE0 - 0xE1
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* [15:05] Reserved
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* [04:04] Device 4 Function 1 Present
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* 0 == Present
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* 1 == Absent
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* [03:03] Device 3 Function 1 Present
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* 0 == Present
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* 1 == Absent
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* [02:02] Device 2 Function 1 Present
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* 0 == Present
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* 1 == Absent
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* [01:01] Reserved
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* [00:00] Device 0 Function 1 Present
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* 0 == Present
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* 1 == Absent
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*/
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0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
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0xd8, 0xffff9fff, 0x00000000,
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0xf4, 0x3f8ffffd, 0x40300002,
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0x1050, 0xffffffcf, 0x00000030,
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};
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@ -494,9 +396,9 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
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#endif
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/*enable access to the rcomp bar */
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/* for e7501 they also set bit 31 ... */
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dword = pci_read_config32(ctrl->d0, 0x0f4);
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dword &= ~(1<<31);
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dword |=((1<<30)|1<<22);
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dword |= 1<<22;
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pci_write_config32(ctrl->d0, 0x0f4, dword);
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@ -507,7 +409,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
|
|||
dword |= (1<<9);
|
||||
write32(RCOMP_MMIO + 0x20, dword);
|
||||
|
||||
|
||||
#ifdef NOTNOW
|
||||
/* Begin to write the RCOMP registers */
|
||||
|
||||
write8(RCOMP_MMIO + 0x2c, 0xff);
|
||||
|
|
@ -564,7 +466,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
|
|||
|
||||
/* Wait 40 usec */
|
||||
SLOW_DOWN_IO;
|
||||
|
||||
#endif
|
||||
/*disable access to the rcomp bar */
|
||||
dword = pci_read_config32(ctrl->d0, 0x0f4);
|
||||
dword &= ~(1<<22);
|
||||
|
|
|
|||
Loading…
Reference in New Issue