GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/var/felwinter: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
felwinter boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-07 15:37:39 +08:00 committed by Felix Held
parent facdd7e04c
commit 43e8807b6f
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/mainboard/google/brya/variants/felwinter/gpio.c
View File

@ -12,31 +12,31 @@ static const struct pad_config override_gpio_table[] = {
/* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */ /* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */
PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE), PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE),
/* B3 : PROC_GP2 ==> NC */ /* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE), PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
/* B5 : ISH_I2C0_SDA ==> NC */ /* B5 : ISH_I2C0_SDA ==> NC */
PAD_NC(GPP_B5, NONE), PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
/* B6 : ISH_I2C0_SCL ==> NC */ /* B6 : ISH_I2C0_SCL ==> NC */
PAD_NC(GPP_B6, NONE), PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
/* B6 : TIME_SYNC0 ==> NC */ /* B6 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE), PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */ /* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> EN_PP5000_PEN */ /* C4 : SML0DATA ==> EN_PP5000_PEN */
PAD_CFG_GPO(GPP_C4, 1, DEEP), PAD_CFG_GPO(GPP_C4, 1, DEEP),
/* D0 : ISH_GP0 ==> NC */ /* D0 : ISH_GP0 ==> NC */
PAD_NC(GPP_D0, NONE), PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> NC */ /* D1 : ISH_GP1 ==> NC */
PAD_NC(GPP_D1, NONE), PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> NC */ /* D2 : ISH_GP2 ==> NC */
PAD_NC(GPP_D2, NONE), PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NC */ /* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE), PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> NC */ /* D5 : SRCCLKREQ0# ==> NC */
PAD_NC(GPP_D5, NONE), PAD_NC(GPP_D5, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */ /* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE), PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */ /* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE), PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* E0 : SATAXPCIE0 ==> NC */ /* E0 : SATAXPCIE0 ==> NC */
PAD_NC(GPP_E0, NONE), PAD_NC(GPP_E0, NONE),
/* E3 : PROC_GP0 ==> NC */ /* E3 : PROC_GP0 ==> NC */
@ -44,13 +44,13 @@ static const struct pad_config override_gpio_table[] = {
/* E7 : PROC_GP1 ==> NC */ /* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* E9 : USB_OC0# ==> NC */ /* E9 : USB_OC0# ==> NC */
PAD_NC(GPP_E9, NONE), PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
/* E10 : THC0_SPI1_CS# ==> NC */ /* E10 : THC0_SPI1_CS# ==> NC */
PAD_NC(GPP_E10, NONE), PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E16 : RSVD_TP ==> NC */ /* E16 : RSVD_TP ==> NC */
PAD_NC(GPP_E16, NONE), PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */ /* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE), PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> NC */ /* E18 : DDP1_CTRLCLK ==> NC */
PAD_NC(GPP_E18, NONE), PAD_NC(GPP_E18, NONE),
/* E22 : DDPA_CTRLCLK ==> NC */ /* E22 : DDPA_CTRLCLK ==> NC */
@ -60,15 +60,15 @@ static const struct pad_config override_gpio_table[] = {
/* F6 : CNV_PA_BLANKING ==> NC */ /* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F6, NONE),
/* F11 : THC1_SPI2_CLK ==> NC */ /* F11 : THC1_SPI2_CLK ==> NC */
PAD_NC(GPP_F11, NONE), PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : GSXDOUT ==> NC */ /* F12 : GSXDOUT ==> NC */
PAD_NC(GPP_F12, NONE), PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* F13 : GSXDOUT ==> NC */ /* F13 : GSXDOUT ==> NC */
PAD_NC(GPP_F13, NONE), PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F15 : GSXSRESET# ==> NC */ /* F15 : GSXSRESET# ==> NC */
PAD_NC(GPP_F15, NONE), PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
/* F16 : GSXCLK ==> NC */ /* F16 : GSXCLK ==> NC */
PAD_NC(GPP_F16, NONE), PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F20 : EXT_PWR_GATE# ==> NC */ /* F20 : EXT_PWR_GATE# ==> NC */
PAD_NC(GPP_F20, NONE), PAD_NC(GPP_F20, NONE),
/* F21 : EXT_PWR_GATE2# ==> NC */ /* F21 : EXT_PWR_GATE2# ==> NC */