soc/intel/alderlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -146,12 +146,6 @@ struct soc_intel_alderlake_config {
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/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
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uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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/* Integrated Sensor */
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uint8_t PchIshEnable;
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/* Heci related */
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uint8_t Heci3Enabled;
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/* Gfx related */
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enum {
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IGD_SM_0MB = 0x00,
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@ -178,8 +172,6 @@ struct soc_intel_alderlake_config {
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uint8_t InternalGfx;
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uint8_t SkipExtGfxScan;
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uint32_t GraphicsConfigPtr;
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/* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS */
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uint8_t HeciEnabled;
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