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soc/intel/alderlake: Drop unreferenced devicetree settings

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No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2020-12-11 16:48:10 +01:00 committed by Hung-Te Lin
parent f0fd6aeecd
commit 43e93d7df9
1 changed files with 0 additions and 8 deletions
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8
src/soc/intel/alderlake/chip.h
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@ -146,12 +146,6 @@ struct soc_intel_alderlake_config {
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/* Integrated Sensor */
uint8_t PchIshEnable;
/* Heci related */
uint8_t Heci3Enabled;
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
@ -178,8 +172,6 @@ struct soc_intel_alderlake_config {
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;