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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -206,13 +206,9 @@ static void main(void)
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static const struct ht_chain ht_c[] = {
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{ /* Link 2 of CPU0 */
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.udev = PCI_DEV(0, 0x18, 0),
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.upos = 0xc0,
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.devreg = 0xe0, /* Preset bus num in resource map */
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},
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{ /* Link 1 of CPU1 */
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.udev = PCI_DEV(0, 0x19, 0),
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.upos = 0xa0,
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.devreg = 0xe4, /* Preset bus num in resource map */
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},
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};
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@ -180,13 +180,9 @@ static void main(unsigned long bist)
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#if 1
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static const struct ht_chain ht_c[] = {
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{ /* Link 2 of CPU0 */
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.udev = PCI_DEV(0, 0x18, 0),
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.upos = 0xc0,
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.devreg = 0xe0, /* Preset bus num in resource map */
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},
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{ /* Link 0 of CPU0 */
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.udev = PCI_DEV(0, 0x18, 0),
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.upos = 0x80,
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.devreg = 0xe4, /* Preset bus num in resource map */
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},
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};
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@ -246,8 +246,6 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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}
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struct ht_chain {
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device_t udev;
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unsigned upos;
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unsigned devreg;
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};
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static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
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@ -344,20 +342,24 @@ static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
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dword |= (reg & 0xffff0000)>>8;
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pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
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#if 0
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print_debug("PCI_DEV=(0,0x");
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print_debug("udev=(0,0x");
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print_debug_hex8(devpos);
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print_debug(",0) 0x");
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print_debug_hex8(regpos);
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print_debug("=");
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print_debug_hex32(dword);
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print_debug("\r\n");
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#endif
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/* Make certain the HT bus is not enumerated */
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ht_collapse_previous_enumeration(busn);
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upos = ht_c[i].upos;
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udev = ht_c[i].udev;
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upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
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udev = PCI_DEV(0, devpos, 0);
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#if 0
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print_debug("\tupos=0x");
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print_debug_hex32(upos);
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print_debug("\r\n");
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#endif
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reset_needed |= ht_setup_chainx(udev,upos,busn );
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