mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
Add new memory.c to support DDR4 memory types. Use the new meminit_ddr() and variant_memory_sku() for eldrid variant code on memory.c The initial settings override the baseboard from volteer and fine tune gpio.c and overridetree.cb on eldrid's configuration. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid can boots. NOTE that tests the ddr4 side of the implementation. Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
nick_xr_chen
Patrick Georgi
parent
404a42bb3a
commit
44097e21cc
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += memory.c
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,217 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_A8, 0, DEEP),
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/* A10 : I2S2_RXD ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_A10, 1, DEEP),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_A13, 1, DEEP),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
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/* B2 : VRALERT# ==> EN_PP3300_SSD */
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PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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/* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
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PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
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PAD_CFG_GPI(GPP_C5, NONE, DEEP),
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/* C10 : UART0_RTS# ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C10, 0, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* C20 : UART2_RXD ==> FPMCU_INT_L */
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/* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
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PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */
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PAD_CFG_GPI(GPP_D4, NONE, DEEP),
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/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
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PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_NC(GPP_D13, NONE),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
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PAD_CFG_GPO(GPP_D17, 1, DEEP),
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/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* E3 : CPU_GP0 ==> USI_REPORT_EN */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E4, NONE, DEEP),
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/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
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PAD_CFG_GPI(GPP_E6, NONE, DEEP),
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/* E7 : CPU_GP1 ==> USI_INT */
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
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/* E8 : SPI1_CS1# ==> SLP_S0IX */
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PAD_CFG_GPO(GPP_E8, 0, DEEP),
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/* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
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/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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/* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
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/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
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PAD_CFG_GPO(GPP_E22, 1, DEEP),
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/* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
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PAD_CFG_GPO(GPP_E23, 1, DEEP),
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/* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */
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PAD_CFG_GPI(GPP_F7, NONE, DEEP),
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/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
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PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
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/* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */
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PAD_CFG_GPI(GPP_F10, NONE, DEEP),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> NC */
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PAD_NC(GPP_F12, NONE),
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/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
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PAD_CFG_GPO(GPP_F13, 1, DEEP),
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/* H0 : GPPH0_BOOT_STRAP1 */
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PAD_CFG_GPI(GPP_H0, NONE, DEEP),
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/* H1 : GPPH1_BOOT_STRAP2 */
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PAD_CFG_GPI(GPP_H1, NONE, DEEP),
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/* H2 : GPPH2_BOOT_STRAP3 */
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PAD_CFG_GPI(GPP_H2, NONE, DEEP),
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/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H3, 1, DEEP),
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/* H4 : I2C2_SDA ==> NC */
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PAD_NC(GPP_H4, NONE),
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/* H5 : I2C2_SCL ==> NC */
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PAD_NC(GPP_H5, NONE),
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/* H10 : SRCCLKREQ4# ==> NC */
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PAD_NC(GPP_H10, NONE),
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/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H11, 1, DEEP),
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/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
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/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
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/* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
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/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
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/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
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/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
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/* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */
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PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
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/* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */
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PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
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/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> NC */
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PAD_NC(GPP_E12, NONE),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H11, 1, DEEP),
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */
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static const struct mb_ddr4_cfg eldrid_memcfg = {
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};
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static const struct ddr_memory_cfg baseboard_memcfg = {
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.mem_type = MEMTYPE_DDR4,
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.ddr4_cfg = &eldrid_memcfg
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};
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const struct ddr_memory_cfg *variant_memory_params(void)
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{
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return &baseboard_memcfg;
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}
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int variant_memory_sku(void)
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{
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gpio_t spd_gpios[] = {
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GPIO_MEM_CONFIG_3,
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GPIO_MEM_CONFIG_2,
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GPIO_MEM_CONFIG_1,
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GPIO_MEM_CONFIG_0,
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};
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return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
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}
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@ -3,8 +3,136 @@ chip soc/intel/tigerlake
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C1 | Touchscreen |
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#| I2C2 | WLAN, SAR0 |
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#| I2C3 | Camera, SAR1 |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 163,
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.scl_hcnt = 75,
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.sda_hold = 36,
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},
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},
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}"
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device domain 0 on
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device pci 04.0 off end
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end
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device pci 15.1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""GDIX0000""
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register "generic.desc" = ""Goodix Touchscreen""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
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register "generic.reset_delay_ms" = "120"
|
||||
register "generic.reset_off_delay_ms" = "3"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 14 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN90FC""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.disable_gpio_export_in_crs" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end # I2C1 0xA0E9
|
||||
device pci 19.1 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "probed" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # I2C5 0xA0C6
|
||||
device pci 1f.3 on
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98357A""
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.2 hidden
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
register "usb2_port_number" = "9"
|
||||
register "usb3_port_number" = "1"
|
||||
# SBU & HSL follow CC
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
register "usb2_port_number" = "4"
|
||||
register "usb3_port_number" = "2"
|
||||
# SBU is fixed, HSL follows CC
|
||||
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
device generic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # PMC
|
||||
end
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue