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intel/baytrail: Reorganize romstage.c 

Done just for future review convenience.

Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-16 17:20:40 +03:00 committed by Patrick Georgi
parent 2a3f9f543a
commit 44449192ab
1 changed files with 58 additions and 58 deletions
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116
src/soc/intel/baytrail/romstage/romstage.c
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@ -44,16 +44,6 @@
#include <soc/smm.h>
#include <soc/spi.h>
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
* romstage_common() below. The reason for the back and forth is to provide
* common entry point from cache-as-ram while still allowing for code sharing.
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
static struct postcar_frame early_mtrrs;
static void program_base_addresses(void)
{
uint32_t reg;
@ -99,54 +89,6 @@ static void spi_init(void)
write32(bcr, reg);
}
/* Entry from cache-as-ram.inc. */
static void romstage_main(uint64_t tsc)
{
struct romstage_params rp = {
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init(tsc);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
if (CONFIG(ENABLE_BUILTIN_COM1))
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
/* Call into mainboard. */
mainboard_romstage_entry_rp(&rp);
if (CONFIG(SMM_TSEG))
smm_list_regions();
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
romstage_main(base_timestamp);
}
static struct chipset_power_state power_state;
static void migrate_power_state(int is_recovery)
@ -216,6 +158,56 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
return prev_sleep_state;
}
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
* romstage_common() below. The reason for the back and forth is to provide
* common entry point from cache-as-ram while still allowing for code sharing.
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
static struct postcar_frame early_mtrrs;
/* Entry from cache-as-ram.inc. */
static void romstage_main(uint64_t tsc)
{
struct romstage_params rp = {
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init(tsc);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
if (CONFIG(ENABLE_BUILTIN_COM1))
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
/* Call into mainboard. */
mainboard_romstage_entry_rp(&rp);
if (CONFIG(SMM_TSEG))
smm_list_regions();
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
@ -243,6 +235,14 @@ void romstage_common(struct romstage_params *params)
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
romstage_main(base_timestamp);
}
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;