From 4454c9af3c3d44c4ea3c3dfa9eb58c59385e3778 Mon Sep 17 00:00:00 2001
From: Rob Barnes <robbarnes@google.com>
Date: Fri, 17 Dec 2021 10:37:43 -0700
Subject: [PATCH] soc/amd/cezanne: Correct S0i3 verstage softfuse bit

PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.

BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.

Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 src/soc/amd/cezanne/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index a05da8dc76..050ba44be9 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -111,7 +111,7 @@ PSP_SOFTFUSE_BITS += 29
 endif
 
 ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y)
-PSP_SOFTFUSE_BITS += 40
+PSP_SOFTFUSE_BITS += 58
 endif
 
 # Use additional Soft Fuse bits specified in Kconfig