util/mb/google: add support for nissa
Add the file template for creating a new variant of Nissa. BUG=b:229550821 Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com> Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
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SPD_SOURCES = placeholder
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DRAM Part Name ID to assign
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
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# Generate an updated Makefile.inc and dram_id.generated.txt by running the
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# part_id_gen tool from util/spd_tools.
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# See util/spd_tools/README.md for more details and instructions.
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# Part Name
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chip soc/intel/alderlake
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device domain 0 on
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end
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end
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