esd/atom15: import esd atom15 board
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Michael Tasche
Martin Roth
parent
4d166f9380
commit
446c5dcd14
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@ -0,0 +1,16 @@
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if VENDOR_ESD
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choice
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prompt "Mainboard model"
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source "src/mainboard/esd/*/Kconfig.name"
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endchoice
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source "src/mainboard/esd/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "esd"
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endif # VENDOR_ESD
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@ -0,0 +1,2 @@
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config VENDOR_ESD
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bool "electronic system design"
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@ -0,0 +1,70 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_ESD_ATOM15
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SOC_INTEL_FSP_BAYTRAIL
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select TSC_MONOTONIC_TIMER
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select HAVE_ACPI_RESUME
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config MAINBOARD_DIR
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string
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default "esd/atom15"
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config MAINBOARD_PART_NUMBER
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string
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default "esd atom15"
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config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
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config CBFS_SIZE
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hex
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default 0x00300000
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config ENABLE_FSP_FAST_BOOT
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bool
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depends on HAVE_FSP_BIN
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default y
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config VIRTUAL_ROM_SIZE
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hex
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depends on ENABLE_FSP_FAST_BOOT
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default 0x800000
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config POST_DEVICE
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bool
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default n
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config VGA_BIOS
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bool
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default y if FSP_PACKAGE_DEFAULT
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endif # BOARD_ESD_ATOM15
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@ -0,0 +1,2 @@
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config BOARD_ESD_ATOM15
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bool "Atom15"
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@ -0,0 +1,17 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-y += gpio.c
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ramstage-y += irqroute.c
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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@ -0,0 +1,56 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <lib.h> // hexdump
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <baytrail/acpi.h>
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#include <baytrail/nvs.h>
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#include <baytrail/iomap.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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acpi_init_gnvs(gnvs);
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/* No TPM Present */
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gnvs->tpmp = 0;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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current = acpi_madt_irq_overrides(current);
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return current;
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}
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Category: sbc
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ROM protocol: SPI
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Flashrom support: y
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Release year: 2015
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@ -0,0 +1,116 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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411 2 e 8 use_xhci_over_ehci
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#413 3 r 0 unused
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# MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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#save timestamps in pre-ram boot areas
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1719 64 h 0 timestamp_value1
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1783 64 h 0 timestamp_value2
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1847 64 h 0 timestamp_value3
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1911 64 h 0 timestamp_value4
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1975 64 h 0 timestamp_value5
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 EHCI
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8 1 XHCI
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8 2 Default
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,93 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
|
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_UNSPECIFIED"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
|
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
|
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
|
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
|
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register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
|
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register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
|
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register "DRAMType" = "DRAM_TYPE_DDR3L"
|
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register "DIMM0Enable" = "DIMM0_ENABLE"
|
||||
register "DIMM1Enable" = "DIMM1_DISABLE"
|
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register "DIMMDWidth" = "DIMM_DWIDTH_X16"
|
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register "DIMMDensity" = "DIMM_DENSITY_4G_BIT"
|
||||
register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
|
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register "DIMMSides" = "DIMM_SIDES_1RANK"
|
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register "DIMMtCL" = "8"
|
||||
register "DIMMtRPtRCD" = "8"
|
||||
register "DIMMtWR" = "8"
|
||||
register "DIMMtWTR" = "4"
|
||||
register "DIMMtRRD" = "6"
|
||||
register "DIMMtRTP" = "4"
|
||||
register "DIMMtFAW" = "27"
|
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device cpu_cluster 0 on
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device lapic 0 on end
|
||||
end
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|
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device domain 0 on
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device pci 00.0 on end # 8086 0F00 - SoC router -
|
||||
device pci 02.0 off end # 8086 0F31 - GFX -
|
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device pci 03.0 off end # 8086 0F38 - MIPI -
|
||||
|
||||
device pci 10.0 off end # 8086 0F14 - EMMC Port -
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device pci 11.0 off end # 8086 0F15 - SDIO Port -
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device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
|
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device pci 13.0 off end # 8086 0F23 - SATA AHCI -
|
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device pci 14.0 off end # 8086 0F35 - USB XHCI -
|
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device pci 15.0 off end # 8086 0F28 - LP Engine Audio -
|
||||
device pci 17.0 off end # 8086 0F50 - MMC Port -
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device pci 18.0 on end # 8086 0F40 - SIO - DMA -
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||||
device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) -
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||||
device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) -
|
||||
device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) -
|
||||
device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) -
|
||||
device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) -
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||||
device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) EEPROM
|
||||
device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) -
|
||||
device pci 1a.0 off end # 8086 0F18 - TXE -
|
||||
device pci 1b.0 off end # 8086 0F04 - HD Audio -
|
||||
device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) -
|
||||
device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
|
||||
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET
|
||||
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN
|
||||
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI -
|
||||
device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
|
||||
device pci 1e.1 on end # 8086 0F08 - PWM 1 -
|
||||
device pci 1e.2 on end # 8086 0F09 - PWM 2 -
|
||||
device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart
|
||||
device pci 1e.4 off end # 8086 0F0C - HSUART 2 -
|
||||
device pci 1e.5 off end # 8086 0F0E - SPI -
|
||||
device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
|
||||
device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define INCLUDE_LPE 1
|
||||
#define INCLUDE_SCC 1
|
||||
#define INCLUDE_EHCI 1
|
||||
#define INCLUDE_XHCI 1
|
||||
#define INCLUDE_LPSS 1
|
||||
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include <soc/intel/fsp_baytrail/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
|
||||
|
||||
#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <baytrail/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
acpi_fill_in_fadt(fadt,facs,dsdt);
|
||||
|
||||
/* Platform specific customizations go here */
|
||||
|
||||
header->checksum = 0;
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <baytrail/gpio.h>
|
||||
#include "irqroute.h"
|
||||
|
||||
/*
|
||||
* For multiplexed functions, look in EDS:
|
||||
* 10.3 Ball Name and Function by Location
|
||||
*
|
||||
* The pads list is in the BWG_VOL2 Rev1p2:
|
||||
* Note that Pad # is not the same as GPIO#
|
||||
* 37 GPIO Handling:
|
||||
* Table 37-1. SCORE Pads List
|
||||
* Table 37-2. SSUSORE Pads List
|
||||
*/
|
||||
|
||||
/* NCORE GPIOs */
|
||||
static const struct soc_gpio_map gpncore_gpio_map[] = {
|
||||
GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */
|
||||
GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */
|
||||
GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */
|
||||
GPIO_NC, /* GPIO_S0_NC[03] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[04] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[05] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[06] - No Connect */
|
||||
GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */
|
||||
GPIO_NC, /* GPIO_S0_NC[08] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[09] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[10] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[11] - No Connect */
|
||||
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */
|
||||
GPIO_NC, /* GPIO_S0_NC[13] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[14] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[15] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[16] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[17] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[18] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[19] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[20] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[21] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[22] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[23] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[24] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[25] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_NC[26] - No Connect */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
/* SCORE GPIOs (GPIO_S0_SC_XX)*/
|
||||
static const struct soc_gpio_map gpscore_gpio_map[] = {
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */
|
||||
GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */
|
||||
GPIO_NC, /* GPIO_S0_SC[008] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[009] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[010] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[011] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[012] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[013] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[014] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[015] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[016] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[017] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[018] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[019] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[020] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[021] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[022] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[023] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[024] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[025] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[026] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[027] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[028] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[029] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[030] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[031] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[032] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[040] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[041] - /SD3_PWREN */
|
||||
GPIO_NC, /* GPIO_S0_SC[042] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[043] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[044] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[045] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[046] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[047] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[048] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[049] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[050] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */
|
||||
GPIO_NC, /* GPIO_S0_SC[055] - No Connect */
|
||||
GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */
|
||||
GPIO_NC, /* GPIO_S0_SC[058] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[059] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[060] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */
|
||||
GPIO_NC, /* GPIO_S0_SC[072] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[073] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[074] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[075] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[076] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[077] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[078] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[079] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[080] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[081] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[082] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[083] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[084] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[085] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[086] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[087] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[088] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[089] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */
|
||||
GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */
|
||||
GPIO_NC, /* GPIO_S0_SC[096] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[097] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[098] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[099] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[100] - No Connect */
|
||||
GPIO_NC, /* GPIO_S0_SC[101] - No Connect */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
/* SSUS GPIOs (GPIO_S5) */
|
||||
static const struct soc_gpio_map gpssus_gpio_map[] = {
|
||||
GPIO_NC, /* GPIO_S5[00] - No Connect */
|
||||
GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */
|
||||
GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */
|
||||
GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */
|
||||
GPIO_NC, /* GPIO_S5[04] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[05] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[06] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[07] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[08] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[09] - No Connect */
|
||||
GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
|
||||
GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK */
|
||||
GPIO_NC, /* GPIO_S5[12] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[13] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */
|
||||
GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */
|
||||
GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[17] - No Connect */
|
||||
GPIO_FUNC1, /* GPIO_S5[18] - T360 */
|
||||
GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */
|
||||
GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */
|
||||
GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */
|
||||
GPIO_NC, /* GPIO_S5[22] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[23] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[24] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[25] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[26] - No Connect */
|
||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - SW450-1 */
|
||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - SW450-2 */
|
||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - SW450-3 */
|
||||
GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */
|
||||
GPIO_NC, /* GPIO_S5[31] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[32] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[33] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[34] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[35] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[36] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[37] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[38] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[39] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[40] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[41] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[42] - No Connect */
|
||||
GPIO_NC, /* GPIO_S5[43] - No Connect */
|
||||
GPIO_END
|
||||
};
|
||||
|
||||
static struct soc_gpio_config gpio_config = {
|
||||
.ncore = gpncore_gpio_map,
|
||||
.score = gpscore_gpio_map,
|
||||
.ssus = gpssus_gpio_map,
|
||||
.core_dirq = NULL,
|
||||
.sus_dirq = NULL,
|
||||
};
|
||||
|
||||
struct soc_gpio_config* mainboard_get_gpios(void)
|
||||
{
|
||||
return &gpio_config;
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "irqroute.h"
|
||||
|
||||
DEFINE_IRQ_ROUTES;
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef IRQROUTE_H
|
||||
#define IRQROUTE_H
|
||||
|
||||
#include <soc/intel/fsp_baytrail/baytrail/irq.h>
|
||||
#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
|
||||
|
||||
/*
|
||||
*IR02h GFX INT(A) - PIRQ A
|
||||
*IR10h EMMC INT(ABCD) - PIRQ DEFG
|
||||
*IR11h SDIO INT(A) - PIRQ B
|
||||
*IR12h SD INT(A) - PIRQ C
|
||||
*IR13h SATA INT(A) - PIRQ D
|
||||
*IR14h XHCI INT(A) - PIRQ E
|
||||
*IR15h LP Audio INT(A) - PIRQ F
|
||||
*IR17h MMC INT(A) - PIRQ F
|
||||
*IR18h SIO INT(ABCD) - PIRQ BADC
|
||||
*IR1Ah TXE INT(A) - PIRQ F
|
||||
*IR1Bh HD Audio INT(A) - PIRQ G
|
||||
*IR1Ch PCIe INT(ABCD) - PIRQ EFGH
|
||||
*IR1Dh EHCI INT(A) - PIRQ D
|
||||
*IR1Eh SIO INT(ABCD) - PIRQ BDEF
|
||||
*IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
||||
*/
|
||||
|
||||
/* PCIe bridge routing */
|
||||
#define BRIDGE1_DEV PCIE_DEV
|
||||
|
||||
/* PCI bridge IRQs need to be updated in both tables and need to match */
|
||||
#define PCIE_BRIDGE_IRQ_ROUTES \
|
||||
PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
|
||||
|
||||
#define PCI_DEV_PIRQ_ROUTES \
|
||||
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
|
||||
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
|
||||
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
|
||||
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
||||
|
||||
/*
|
||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
||||
* Reserved: 0, 1, 2, 8, 13
|
||||
* PS2 keyboard: 12
|
||||
* ACPI/SCI: 9
|
||||
* Floppy: 6
|
||||
*/
|
||||
#define PIRQ_PIC_ROUTES \
|
||||
PIRQ_PIC(A, 3), \
|
||||
PIRQ_PIC(B, 5), \
|
||||
PIRQ_PIC(C, 7), \
|
||||
PIRQ_PIC(D, 10), \
|
||||
PIRQ_PIC(E, 11), \
|
||||
PIRQ_PIC(F, 12), \
|
||||
PIRQ_PIC(G, 14), \
|
||||
PIRQ_PIC(H, 15)
|
||||
|
||||
#endif /* IRQROUTE_H */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
/*
|
||||
* mainboard_enable is executed as first thing after enumerate_buses().
|
||||
* This is the earliest point to add customization.
|
||||
*/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* mainboard_final is executed as one of the last items before loading the
|
||||
* payload.
|
||||
*
|
||||
* This is the latest point to add customization.
|
||||
*/
|
||||
static void mainboard_final(void *chip_info)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
.final = mainboard_final,
|
||||
};
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
||||
* Copyright (C) 2014 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baytrail/romstage.h>
|
||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include <baytrail/gpio.h>
|
||||
#include "chip.h"
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done before fsp init
|
||||
*
|
||||
*/
|
||||
void early_mainboard_romstage_entry()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Get function disables - most of these will be done automatically
|
||||
* @param fd_mask
|
||||
* @param fd2_mask
|
||||
*/
|
||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done after fsp init
|
||||
*
|
||||
*/
|
||||
void late_mainboard_romstage_entry()
|
||||
{
|
||||
|
||||
configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
||||
configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
||||
configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
||||
configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
|
||||
|
||||
printk(0, "SW450: %d %d %d %d\n",
|
||||
read_ssus_gpio(27),
|
||||
read_ssus_gpio(28),
|
||||
read_ssus_gpio(29),
|
||||
read_ssus_gpio(30) );
|
||||
|
||||
}
|
||||
|
||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
||||
{
|
||||
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
|
||||
u8 use_xhci = UpdData->PcdEnableXhci;
|
||||
|
||||
/* Update XHCI UPD value if required */
|
||||
get_option(&use_xhci, "use_xhci_over_ehci");
|
||||
if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
|
||||
UpdData->PcdEnableXhci = use_xhci;
|
||||
printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
|
||||
UpdData->PcdEnableXhci?"Enabled":"Disabled");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
Loading…
Reference in New Issue