broadwell: Misc updates from 2.1.0 ref code

- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/broadwell/acpi/adsp.asl

@@ -36,12 +36,12 @@ Device (ADSP)
 	{
 		Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0)
 		Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {3}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3}
 	})
 
 	Method (_CRS, 0, NotSerialized)
 	{
-		// Update BAR0 address and length if set in NVS
+		// Update BAR address and length if set in NVS
 		If (LNotEqual (\S8B0, Zero)) {
 			CreateDwordField (^RBUF, ^BAR0._BAS, B8A0)
 			CreateDwordField (^RBUF, ^BAR1._BAS, B8A1)
@@ -60,4 +60,14 @@ Device (ADSP)
 			Return (0xF)
 		}
 	}
+
+	Device (I2S0)
+	{
+		Name (_ADR, 0)
+	}
+
+	Device (I2S1)
+	{
+		Name (_ADR, 1)
+	}
 }

src/soc/intel/broadwell/broadwell/rcba.h

@@ -122,6 +122,16 @@
 #define D19IR		0x3168	/* 16bit */
 #define ACPIIRQEN	0x31e0	/* 32bit */
 #define OIC		0x31fe	/* 16bit */
+#define DEEP_S3_POL	0x3328	/* 32bit */
+#define  DEEP_S3_EN_AC		(1 << 0)
+#define  DEEP_S3_EN_DC		(1 << 1)
+#define DEEP_S5_POL	0x3330	/* 32bit */
+#define  DEEP_S5_EN_AC		(1 << 14)
+#define  DEEP_S5_EN_DC		(1 << 15)
+#define DEEP_SX_CONFIG	0x3334	/* 32bit */
+#define  DEEP_SX_WAKE_PIN_EN	(1 << 2)
+#define  DEEP_SX_ACPRESENT_PD	(1 << 1)
+#define  DEEP_SX_GP27_PIN_EN	(1 << 0)
 #define PMSYNC_CONFIG	0x33c4	/* 32bit */
 #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
 #define SOFT_RESET_CTRL 0x38f4

src/soc/intel/broadwell/chip.h

@@ -129,6 +129,10 @@ struct soc_intel_broadwell_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 
+	/* Deep SX enable */
+	int deep_sx_enable_ac;
+	int deep_sx_enable_dc;
+
 	/* TCC activation offset */
 	int tcc_offset;
 };

src/soc/intel/broadwell/hda.c

@@ -79,10 +79,6 @@ static void hda_pch_init(struct device *dev, u8 *base)
 		pci_write_config32(dev, 0x120, reg32);
 	}
 
-	reg8 = pci_read_config8(dev, 0x43);
-	reg8 &= ~(1 << 6);
-	pci_write_config8(dev, 0x43, reg8);
-
 	/* Additional programming steps */
 	reg32 = pci_read_config32(dev, 0xc4);
 	reg32 |= (1 << 24);
@@ -138,12 +134,17 @@ static void hda_init(struct device *dev)
 static void hda_enable(struct device *dev)
 {
 	u32 reg32;
+	u8 reg8;
+
+	reg8 = pci_read_config8(dev, 0x43);
+	reg8 |= 0x6f;
+	pci_write_config8(dev, 0x43, reg8);
 
 	if (!dev->enabled) {
 		/* Route I/O buffers to ADSP function */
-		reg32 = pci_read_config32(dev, 0x42);
+		reg8 = pci_read_config8(dev, 0x42);
-		reg32 |= (1 << 7) | (1 << 6);
+		reg8 |= (1 << 7) | (1 << 6);
-		pci_write_config32(dev, 0x42, reg32);
+		pci_write_config8(dev, 0x42, reg8);
 
 		printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n");
 

src/soc/intel/broadwell/lpc.c

@@ -205,7 +205,7 @@ static const struct reg_script pch_misc_init_script[] = {
 	/* Enable BIOS updates outside of SMM */
 	REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
 	/* Clear status bits to prevent unexpected wake */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x00000031),
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f),
 	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0),
 	/* Setup SERIRQ, enable continuous mode */
 	REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
@@ -256,6 +256,7 @@ static const struct reg_script pch_pm_init_script[] = {
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
+	/* Power Optimizer */
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
@@ -306,17 +307,42 @@ static void pch_enable_mphy(void)
 	pch_iobp_update(0xCF000000, data_and, data_or);
 }
 
+static void pch_init_deep_sx(struct device *dev)
+{
+	config_t *config = dev->chip_info;
+
+	if (config->deep_sx_enable_ac) {
+		RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
+		RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_AC);
+	}
+
+	if (config->deep_sx_enable_dc) {
+		RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_DC);
+		RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_DC);
+	}
+
+	if (config->deep_sx_enable_ac || config->deep_sx_enable_dc)
+		RCBA32_OR(DEEP_SX_CONFIG,
+			  DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN);
+}
+
 /* Power Management init */
 static void pch_pm_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "PCH PM init\n");
 
+	pch_init_deep_sx(dev);
+
 	pch_enable_mphy();
 
 	reg_script_run_on_dev(dev, pch_pm_init_script);
 
-	if (pch_is_wpt())
+	if (pch_is_wpt()) {
 		RCBA32_OR(0x33e0, (1 << 4) | (1 << 1));
+		RCBA32_OR(0x2b1c, (1 << 22) | (1 << 14) | (1 << 13));
+		RCBA32(0x33e4) = 0x16bf0002;
+		RCBA32_OR(0x33e4, 0x1);
+	}
 
 	pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
 
@@ -352,10 +378,10 @@ static void pch_cg_init(device_t dev)
 	 * RCBA + 0x2614[30:28] = 0x0
 	 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
 	 */
-	RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
+	RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500);
 
 	/* Check for 0:2.0@0x08 >= 0x0b */
-	if (pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b)
+	if (pch_is_wpt() || pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b)
 		RCBA32_OR(0x2614, (1 << 26));
 
 	RCBA32_OR(0x900, 0x0000031f);
@@ -367,13 +393,18 @@ static void pch_cg_init(device_t dev)
 		reg32 |= (1 << 29); // LPC Dynamic
 	reg32 |= (1 << 31); // LP LPC
 	reg32 |= (1 << 30); // LP BLA
+	if (RCBA32(0x3454) & (1 << 4))
+		reg32 &= ~(1 << 29);
+	else
+		reg32 |= (1 << 29);
 	reg32 |= (1 << 28); // GPIO Dynamic
 	reg32 |= (1 << 27); // HPET Dynamic
 	reg32 |= (1 << 26); // Generic Platform Event Clock
 	if (RCBA32(BUC) & PCH_DISABLE_GBE)
 		reg32 |= (1 << 23); // GbE Static
+	if (RCBA32(FD) & PCH_DISABLE_HD_AUDIO)
+		reg32 |= (1 << 21); // HDA Static
 	reg32 |= (1 << 22); // HDA Dynamic
-	reg32 |= (1 << 16); // PCI Dynamic
 	RCBA32(CG) = reg32;
 
 	/* PCH-LP LPC */
@@ -382,9 +413,6 @@ static void pch_cg_init(device_t dev)
 	else
 		RCBA32_OR(0x3434, 0x7);
 
-	/* SATA */
-	RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000);
-
 	/* SPI */
 	RCBA32_OR(0x38c0, 0x3c07);
 

src/soc/intel/broadwell/pcie.c

@@ -226,6 +226,9 @@ static void pcie_enable_clock_gating(void)
 		/* Configure shared resource clock gating. */
 		if (rp == 1 || rp == 5 || rp == 6)
 			pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c);
+
+		/* CLKREQ# VR Idle Enable */
+		RCBA32_OR(0x2b1c, (1 << (16 + i)));
 	}
 
 	if (!enabled_ports)

src/soc/intel/broadwell/sata.c

@@ -211,9 +211,10 @@ static void sata_init(struct device *dev)
 	sir_write(dev, 0x70, 0x3f00bf1f);
 	sir_write(dev, 0x54, 0xcf000f0f);
 	sir_write(dev, 0x58, 0x00190000);
+	RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000);
 
 	reg32 = pci_read_config32(dev, 0x300);
-	reg32 |= (1 << 17) | (1 << 16);
+	reg32 |= (1 << 17) | (1 << 16) | (1 << 19);
 	reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
 	pci_write_config32(dev, 0x300, reg32);
 }