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rambi: add all on-board devices 

Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
     southcluster disable function.

Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4912
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Aaron Durbin 2013-10-29 17:00:07 -05:00 committed by Aaron Durbin
parent d7bc23ac8e
commit 4477050e22
1 changed files with 31 additions and 3 deletions
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34
src/mainboard/google/rambi/devicetree.cb
View File

@ -3,8 +3,36 @@ chip soc/intel/baytrail
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 1f.0 on end # LPC Bridge
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 on end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 on end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 on end # HSUART2
device pci 1e.5 on end # SPI
device pci 1f.0 on end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end