soc/amd/common: Add common function to get cpu count
This is the same for all supported AMD hardware. Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/msr.h>
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@ -57,7 +58,7 @@ static void model_14_init(struct device *dev)
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mca_clear_status();
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mca_clear_status();
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#if CONFIG(LOGICAL_CPUS)
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#if CONFIG(LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/msr.h>
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@ -59,7 +60,7 @@ static void model_15_init(struct device *dev)
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mca_clear_status();
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mca_clear_status();
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#if CONFIG(LOGICAL_CPUS)
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#if CONFIG(LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/msr.h>
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@ -57,7 +58,7 @@ static void model_16_init(struct device *dev)
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mca_clear_status();
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mca_clear_status();
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#if CONFIG(LOGICAL_CPUS)
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#if CONFIG(LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <amdblocks/smm.h>
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#include <commonlib/helpers.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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@ -25,7 +26,7 @@ static void model_16_init(struct device *dev)
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mca_clear_status();
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mca_clear_status();
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if (CONFIG(LOGICAL_CPUS)) {
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if (CONFIG(LOGICAL_CPUS)) {
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siblings = cpuid_ecx(0x80000008) & 0xff;
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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@ -23,6 +23,7 @@
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#include <northbridge/amd/nb_common.h>
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#include <northbridge/amd/nb_common.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <southbridge/amd/pi/hudson/pci_devs.h>
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#include <southbridge/amd/pi/hudson/pci_devs.h>
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#include <amdblocks/cpu.h>
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#define MAX_NODE_NUMS MAX_NODES
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#define MAX_NODE_NUMS MAX_NODES
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#define PCIE_CAP_AER BIT(5)
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#define PCIE_CAP_AER BIT(5)
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@ -873,13 +874,6 @@ static void pre_mp_init(void)
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x86_mtrr_check();
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x86_mtrr_check();
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}
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}
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static int get_cpu_count(void)
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{
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uint8_t siblings = cpuid_ecx(0x80000008) & 0xff;
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return siblings + 1;
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}
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static const struct mp_ops mp_ops = {
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_cpu_count = get_cpu_count,
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@ -1,5 +1,7 @@
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subdirs-y += ./*
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subdirs-y += ./*
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c
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romstage-y += cpu.c
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ramstage-y += cpu.c
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y)
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y)
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define add-ucode-as-cbfs
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define add-ucode-as-cbfs
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cpu.h>
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#include <amdblocks/cpu.h>
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int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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#include <smbios.h>
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#include <smbios.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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unsigned int smbios_processor_family(struct cpuid_result res)
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unsigned int smbios_processor_family(struct cpuid_result res)
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{
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{
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return 0x6b; /* Zen */
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return 0x6b; /* Zen */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <amdblocks/iomap.h>
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#include <amdblocks/iomap.h>
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#include <amdblocks/mca.h>
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#include <amdblocks/mca.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/reset.h>
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@ -42,11 +43,6 @@ static void pre_mp_init(void)
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x86_mtrr_check();
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x86_mtrr_check();
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}
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}
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static int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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static const struct mp_ops mp_ops = {
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_cpu_count = get_cpu_count,
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