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nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change 

When more than one DIMM is installed on a DCT, only the first DIMM
delay values are scaled to the new memory clock frequency after a
memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-04-22 22:16:45 -05:00
parent 7501b6c285
commit 4488d7371a
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
View File

@ -1212,7 +1212,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
((pDCTData->WLGrossDelayPrevPass[lane_count*dimm+ByteLane] & 0x1f) << 5);
SeedTotalPreScaling[ByteLane] = (SeedTotal[ByteLane] - RegisterDelay - (0x20 * WrDqDqsEarly));
SeedTotal[ByteLane] = (int32_t) (RegisterDelay + ((((int64_t) SeedTotalPreScaling[ByteLane]) *
fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq] * 100)));
fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq[dimm]] * 100)));
}
/* Generate register values from seeds */
@ -1326,7 +1326,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
}
}
pDCTData->WLPrevMemclkFreq = MemClkFreq;
pDCTData->WLPrevMemclkFreq[dimm] = MemClkFreq;
setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 0, pass, lane_count);
}

2
src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
View File

@ -145,7 +145,7 @@ typedef struct _sDCTStruct
int32_t WLCriticalGrossDelayFirstPass;
int32_t WLCriticalGrossDelayPrevPass;
int32_t WLCriticalGrossDelayFinalPass;
uint16_t WLPrevMemclkFreq;
uint16_t WLPrevMemclkFreq[MAX_TOTAL_DIMMS];
u16 RegMan1Present;
u8 DimmPresent[MAX_TOTAL_DIMMS];/* Indicates which DIMMs are present */
/* from Total Number of DIMMs(per Node)*/