From 448ecc0e0660f111b3932368a950f18dae01f578 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Wed, 14 Oct 2020 05:29:09 +0000 Subject: [PATCH] soc/intel/{cnl,skl}: Add alignment check for TSEG base and size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG base and size) to remaining SoCs. Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/smmrelocate.c | 6 ++++++ src/soc/intel/skylake/smmrelocate.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 05bd1f7730..7d189eadf2 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -152,6 +152,12 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 05bd1f7730..7d189eadf2 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -152,6 +152,12 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */