device/dram: use global DIMM_SPD_SIZE Kconfig variable
Also make sure that no board changes behaviour because of that by adding a static assert. TEST=abuild over all builds still succeeds (where it doesn't if DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the device/dram code). Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -1236,7 +1236,6 @@ config DIMM_MAX
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config DIMM_SPD_SIZE
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config DIMM_SPD_SIZE
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int
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int
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default 256
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default 256
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depends on GENERIC_SPD_BIN
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help
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help
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Total SPD size that will be used for DIMM.
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Total SPD size that will be used for DIMM.
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Ex: DDR3 256, DDR4 512.
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Ex: DDR3 256, DDR4 512.
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@ -25,11 +25,13 @@
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#define SPD_CRC_HI 127
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#define SPD_CRC_HI 127
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#define SPD_CRC_LO 126
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#define SPD_CRC_LO 126
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_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ");
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int read_spd_from_cbfs(u8 *buf, int idx)
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int read_spd_from_cbfs(u8 *buf, int idx)
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{
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{
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const char *spd_file;
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const char *spd_file;
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size_t spd_file_len = 0;
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size_t spd_file_len = 0;
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size_t min_len = (idx + 1) * SPD_SIZE;
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size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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&spd_file_len);
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@ -40,9 +42,9 @@ int read_spd_from_cbfs(u8 *buf, int idx)
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if (!spd_file || spd_file_len < min_len)
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if (!spd_file || spd_file_len < min_len)
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return -1;
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return -1;
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memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE);
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memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE);
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u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE);
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u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
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if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
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if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
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|| (buf[SPD_CRC_LO] != (crc & 0xff))
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|| (buf[SPD_CRC_LO] != (crc & 0xff))
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@ -53,7 +55,7 @@ int read_spd_from_cbfs(u8 *buf, int idx)
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buf[SPD_CRC_HI] = crc >> 8;
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buf[SPD_CRC_HI] = crc >> 8;
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u16 i;
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u16 i;
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printk(BIOS_WARNING, "\nDisplay the SPD");
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printk(BIOS_WARNING, "\nDisplay the SPD");
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for (i = 0; i < SPD_SIZE; i++) {
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for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
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if((i % 16) == 0x00)
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if((i % 16) == 0x00)
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printk(BIOS_WARNING, "\n%02x: ", i);
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printk(BIOS_WARNING, "\n%02x: ", i);
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printk(BIOS_WARNING, "%02x ", buf[i]);
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printk(BIOS_WARNING, "%02x ", buf[i]);
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@ -53,4 +53,8 @@ config HUDSON_LEGACY_FREE
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bool
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bool
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default y
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default y
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_AMD_DB_FT3B_LC
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endif # BOARD_AMD_DB_FT3B_LC
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@ -80,4 +80,8 @@ config BAP_E20_DDR3_1066
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endchoice
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endchoice
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_ODE_E20XX
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endif # BOARD_ODE_E20XX
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@ -74,4 +74,8 @@ config BAP_E21_DDR3_1333
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endchoice
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endchoice
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_ODE_E21XX
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endif # BOARD_ODE_E21XX
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@ -70,4 +70,8 @@ config SB800_AHCI_ROM
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bool
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bool
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default n
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default n
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_GIZMOSPHERE_GIZMO
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endif # BOARD_GIZMOSPHERE_GIZMO
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@ -61,4 +61,8 @@ config HUDSON_LEGACY_FREE
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bool
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bool
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default y
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default y
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_GIZMOSPHERE_GIZMO2
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endif # BOARD_GIZMOSPHERE_GIZMO2
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@ -116,4 +116,8 @@ endchoice
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config UART_D_RS485
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config UART_D_RS485
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bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
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bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_PCENGINES_APU1
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endif # BOARD_PCENGINES_APU1
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@ -88,4 +88,8 @@ config APU2_PINMUX_UART_D
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endchoice
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endchoice
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_PCENGINES_APU2
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endif # BOARD_PCENGINES_APU2
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