Kconfig: Bring HEAP_SIZE to a common, large value
We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Patrick Georgi
parent
42f15054b1
commit
44a48ce7a4
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@ -751,8 +751,7 @@ config RTC
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config HEAP_SIZE
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hex
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default 0x100000 if FLATTENED_DEVICE_TREE
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default 0x4000
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default 0x100000
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config STACK_SIZE
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hex
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@ -35,7 +35,4 @@ config MAX_CPUS
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default 32 if SMM_TSEG
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default 4
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config HEAP_SIZE
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default 0x8000
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endif
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@ -10,9 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
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select FLATTENED_DEVICE_TREE
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select SPI_SDCARD
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config HEAP_SIZE
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default 0x10000
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config MAINBOARD_DIR
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default "sifive/hifive-unleashed"
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@ -29,8 +29,4 @@ config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config HEAP_SIZE
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hex
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default 0xc0000
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endif # NORTHBRIDGE_AMD_PI
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@ -264,10 +264,6 @@ config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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@ -152,10 +152,6 @@ config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config EHCI_BAR
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hex
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default 0xfef00000
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@ -30,9 +30,6 @@ config ARCH_ARMV8_EXTENSION
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int
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default 1
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config HEAP_SIZE
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default 0x10000
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config STACK_SIZE
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default 0x2000
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@ -215,11 +215,6 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x80000 if BMP_LOGO
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default 0x10000
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config GFX_GMA_DEFAULT_MMIO
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default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
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@ -252,10 +252,6 @@ config IFWI_FILE_NAME
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help
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Name of file to store in the IFWI region.
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 6
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@ -160,10 +160,6 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x8000
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config NHLT_DMIC_1CH_16B
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bool
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depends on ACPI_NHLT
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@ -104,10 +104,6 @@ config IED_REGION_SIZE
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hex
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default 0x0
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 7
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@ -106,10 +106,6 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 8
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@ -197,11 +197,6 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x80000 if BMP_LOGO
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default 0x10000
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# Intel recommends reserving the PCIe TBT root port resources as below:
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# - 42 buses
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# - 194 MiB Non-prefetchable memory
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@ -151,10 +151,6 @@ config EXCLUDE_NATIVE_SD_INTERFACE
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help
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If you set this option to n, will not use native SD controller.
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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@ -152,10 +152,6 @@ config IED_REGION_SIZE
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config INTEL_TME
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default n
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config HEAP_SIZE
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hex
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default 0x10000
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config MAX_ROOT_PORTS
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int
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default 24 if SOC_INTEL_TIGERLAKE_PCH_H
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@ -91,10 +91,6 @@ config ECAM_MMCONF_BASE_ADDRESS
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config ECAM_MMCONF_BUS_NUMBER
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default 256
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config HEAP_SIZE
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hex
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default 0x80000
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config HPET_MIN_TICKS
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hex
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default 0x80
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@ -71,10 +71,6 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x7C00
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config HEAP_SIZE
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hex
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default 0x80000
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config STACK_SIZE
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hex
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default 0x4000
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@ -55,10 +55,6 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x7C00
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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@ -79,10 +79,6 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x8c00
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config HEAP_SIZE
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hex
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default 0x80000
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config STACK_SIZE
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hex
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default 0x4000
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@ -57,8 +57,4 @@ config SBL_UTIL_PATH
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help
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Path for utils to combine SBL_ELF and bootblock
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config HEAP_SIZE
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hex
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default 0x8000
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endif
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