CONFIG_CHIP_NAME to control config chip.h without .name
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
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7a9c836f93
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44b34e31a5
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@ -1,3 +1,9 @@
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#config chip.h
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uses CONFIG_CHIP_NAME
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#object socket_940.o
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if CONFIG_CHIP_NAME
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config chip.h
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end
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object socket_940.o
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dir /cpu/amd/model_fxx
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dir /cpu/amd/model_fxx
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@ -1,7 +1,8 @@
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#include <device/device.h>
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#include <device/device.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations cpu_amd_socket_940_ops = {
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struct chip_operations cpu_amd_socket_940_ops = {
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CHIP_NAME("socket 940")
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CHIP_NAME("socket 940")
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};
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};
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#endif
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@ -122,73 +122,77 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2735
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# sample config for tyan/s2735
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chip northbridge/intel/e7501
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chip northbridge/intel/e7501/root_complex
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device pci_domain 0 on
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device pci_domain 0 on
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device pci 0.0 on end
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chip northbridge/intel/e7501
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device pci 0.1 on end
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device pci 0.0 on end
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device pci 2.0 on
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device pci 0.1 on end
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chip southbridge/intel/i82870
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device pci 2.0 on
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device pci 1c.0 on end
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chip southbridge/intel/i82870
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device pci 1d.0 on end
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device pci 1c.0 on end
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device pci 1e.0 on end
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device pci 1d.0 on end
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device pci 1f.0 on end
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device pci 1e.0 on end
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end
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device pci 1f.0 on end
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end
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end
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device pci 6.0 on end
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end
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chip southbridge/intel/i82801er
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device pci 6.0 on end
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device pci 1d.0 on end
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chip southbridge/intel/i82801er
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device pci 1d.1 on end
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device pci 1d.0 on end
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device pci 1d.2 on end
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device pci 1d.1 on end
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device pci 1d.3 on end
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device pci 1d.2 on end
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device pci 1d.7 on end
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device pci 1d.3 on end
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device pci 1e.0 on end
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device pci 1d.7 on end
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device pci 1f.0 on
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device pci 1e.0 on end
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device pci 1f.0 on
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# device pci 8.0 end
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# device pci 8.0 end
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chip superio/winbond/w83627hf
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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io 0x60 = 0x3f0
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irq 0x70 = 6
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irq 0x70 = 6
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drq 0x74 = 2
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drq 0x74 = 2
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end
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end
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device pnp 2e.1 off # Parallel Port
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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io 0x60 = 0x378
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irq 0x70 = 7
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irq 0x70 = 7
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end
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end
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device pnp 2e.2 on # Com1
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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io 0x60 = 0x3f8
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irq 0x70 = 4
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irq 0x70 = 4
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end
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end
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device pnp 2e.3 off # Com2
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0x70 = 3
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end
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end
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device pnp 2e.5 on # Keyboard
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x60 = 0x60
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io 0x62 = 0x64
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x70 = 1
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irq 0x72 = 12
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irq 0x72 = 12
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end
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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io 0x60 = 0x290
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end
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end
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end
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end
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end
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end
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device pci 1f.1 off end
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device pci 1f.1 off end
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device pci 1f.2 on end
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device pci 1f.2 on end
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device pci 1f.3 on end
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device pci 1f.3 on end
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device pci 1f.5 off end
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device pci 1f.5 off end
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device pci 1f.6 off end
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device pci 1f.6 off end
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end # SB
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end
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end #NB
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end
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end # PCI_DOMAIN
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device apic_cluster 0 on
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_533Mhz
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chip cpu/intel/socket_mPGA604_533Mhz
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device apic 0 on end
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device apic 0 on end
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@ -44,11 +44,13 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_UDELAY_TSC
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CROSS_COMPILE
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uses CC
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uses CC
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uses HOSTCC
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uses HOSTCC
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uses OBJCOPY
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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###
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###
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### Build options
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### Build options
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@ -5,6 +5,8 @@
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2735_ops = {
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struct chip_operations mainboard_tyan_s2735_ops = {
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CHIP_NAME("Tyan s2735 mainboard")
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CHIP_NAME("Tyan s2735 mainboard")
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};
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};
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#endif
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@ -121,7 +121,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2850
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# sample config for tyan/s2850
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2850_ops = {
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struct chip_operations mainboard_tyan_s2850_ops = {
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CHIP_NAME("Tyan s2850 mainboard")
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CHIP_NAME("Tyan s2850 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2875
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# sample config for tyan/s2875
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2875_ops = {
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struct chip_operations mainboard_tyan_s2875_ops = {
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CHIP_NAME("Tyan s2875 mainboard")
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CHIP_NAME("Tyan s2875 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2880
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# sample config for tyan/s2880
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2880_ops = {
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struct chip_operations mainboard_tyan_s2880_ops = {
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CHIP_NAME("Tyan s2880 mainboard")
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CHIP_NAME("Tyan s2880 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2881
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# sample config for tyan/s2881
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2881_ops = {
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struct chip_operations mainboard_tyan_s2881_ops = {
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CHIP_NAME("Tyan s2881 mainboard")
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CHIP_NAME("Tyan s2881 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2882
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# sample config for tyan/s2882
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2882_ops = {
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struct chip_operations mainboard_tyan_s2882_ops = {
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CHIP_NAME("Tyan s2882 mainboard")
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CHIP_NAME("Tyan s2882 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2885
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# sample config for tyan/s2885
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s2885_ops = {
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struct chip_operations mainboard_tyan_s2885_ops = {
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CHIP_NAME("Tyan s2885 mainboard")
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CHIP_NAME("Tyan s2885 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s4880
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# sample config for tyan/s4880
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s4880_ops = {
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struct chip_operations mainboard_tyan_s4880_ops = {
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CHIP_NAME("Tyan s4880 mainboard")
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CHIP_NAME("Tyan s4880 mainboard")
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};
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};
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#endif
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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##
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dir /pc80
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dir /pc80
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s4882
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# sample config for tyan/s4882
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chip northbridge/amd/amdk8/root_complex
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chip northbridge/amd/amdk8/root_complex
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "chip.h"
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations mainboard_tyan_s4882_ops = {
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struct chip_operations mainboard_tyan_s4882_ops = {
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CHIP_NAME("Tyan s4882 mainboard")
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CHIP_NAME("Tyan s4882 mainboard")
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};
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};
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#endif
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uses CONFIG_CHIP_NAME
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uses AGP_APERTURE_SIZE
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uses AGP_APERTURE_SIZE
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default AGP_APERTURE_SIZE=0x4000000
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default AGP_APERTURE_SIZE=0x4000000
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config chip.h
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if CONFIG_CHIP_NAME
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config chip.h
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end
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object northbridge.o
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object northbridge.o
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driver misc_control.o
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driver misc_control.o
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@ -488,12 +488,15 @@ static struct pci_driver mcf0_driver __pci_driver = {
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.device = 0x1100,
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.device = 0x1100,
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};
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};
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#if CONFIG_CHIP_NAME == 1
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struct chip_operations northbridge_amd_amdk8_ops = {
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struct chip_operations northbridge_amd_amdk8_ops = {
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CHIP_NAME("AMD K8 Northbridge")
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CHIP_NAME("AMD K8 Northbridge")
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.enable_dev = 0,
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.enable_dev = 0,
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};
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};
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#endif
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static void pci_domain_read_resources(device_t dev)
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static void pci_domain_read_resources(device_t dev)
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{
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{
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struct resource *resource;
|
struct resource *resource;
|
||||||
|
|
|
@ -1,4 +1,7 @@
|
||||||
config chip.h
|
uses CONFIG_CHIP_NAME
|
||||||
object northbridge.o
|
|
||||||
#driver misc_control.o
|
|
||||||
|
|
||||||
|
if CONFIG_CHIP_NAME
|
||||||
|
config chip.h
|
||||||
|
end
|
||||||
|
|
||||||
|
object northbridge.o
|
||||||
|
|
|
@ -8,186 +8,8 @@
|
||||||
#include <bitops.h>
|
#include <bitops.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
|
||||||
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
|
#if CONFIG_CHIP_NAME
|
||||||
|
|
||||||
static void pci_domain_read_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource *resource;
|
|
||||||
unsigned reg;
|
|
||||||
|
|
||||||
/* Initialize the system wide io space constraints */
|
|
||||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
|
||||||
resource->limit = 0xffffUL;
|
|
||||||
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
|
||||||
|
|
||||||
/* Initialize the system wide memory resources constraints */
|
|
||||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
|
||||||
resource->limit = 0xffffffffULL;
|
|
||||||
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ram_resource(device_t dev, unsigned long index,
|
|
||||||
unsigned long basek, unsigned long sizek)
|
|
||||||
{
|
|
||||||
struct resource *resource;
|
|
||||||
|
|
||||||
if (!sizek) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
resource = new_resource(dev, index);
|
|
||||||
resource->base = ((resource_t)basek) << 10;
|
|
||||||
resource->size = ((resource_t)sizek) << 10;
|
|
||||||
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
|
|
||||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tolm_test(void *gp, struct device *dev, struct resource *new)
|
|
||||||
{
|
|
||||||
struct resource **best_p = gp;
|
|
||||||
struct resource *best;
|
|
||||||
best = *best_p;
|
|
||||||
if (!best || (best->base > new->base)) {
|
|
||||||
best = new;
|
|
||||||
}
|
|
||||||
*best_p = best;
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t find_pci_tolm(struct bus *bus)
|
|
||||||
{
|
|
||||||
struct resource *min;
|
|
||||||
uint32_t tolm;
|
|
||||||
min = 0;
|
|
||||||
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
|
|
||||||
tolm = 0xffffffffUL;
|
|
||||||
if (min && tolm > min->base) {
|
|
||||||
tolm = min->base;
|
|
||||||
}
|
|
||||||
return tolm;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void pci_domain_set_resources(device_t dev)
|
|
||||||
{
|
|
||||||
struct resource *resource, *last;
|
|
||||||
device_t mc_dev;
|
|
||||||
uint32_t pci_tolm;
|
|
||||||
|
|
||||||
pci_tolm = find_pci_tolm(&dev->link[0]);
|
|
||||||
mc_dev = dev->link[0].children;
|
|
||||||
if (mc_dev) {
|
|
||||||
/* Figure out which areas are/should be occupied by RAM.
|
|
||||||
* This is all computed in kilobytes and converted to/from
|
|
||||||
* the memory controller right at the edges.
|
|
||||||
* Having different variables in different units is
|
|
||||||
* too confusing to get right. Kilobytes are good up to
|
|
||||||
* 4 Terabytes of RAM...
|
|
||||||
*/
|
|
||||||
uint16_t tolm_r, remapbase_r, remaplimit_r;
|
|
||||||
unsigned long tomk, tolmk;
|
|
||||||
unsigned long remapbasek, remaplimitk;
|
|
||||||
int idx;
|
|
||||||
|
|
||||||
/* Get the value of the highest DRB. This tells the end of
|
|
||||||
* the physical memory. The units are ticks of 64MB
|
|
||||||
* i.e. 1 means 64MB.
|
|
||||||
*/
|
|
||||||
tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
|
|
||||||
/* Compute the top of Low memory */
|
|
||||||
tolmk = pci_tolm >> 10;
|
|
||||||
if (tolmk >= tomk) {
|
|
||||||
/* The PCI hole does not overlap memory
|
|
||||||
* we won't use the remap window.
|
|
||||||
*/
|
|
||||||
tolmk = tomk;
|
|
||||||
remapbasek = 0x3ff << 16;
|
|
||||||
remaplimitk = 0 << 16;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
/* The PCI memory hole overlaps memory
|
|
||||||
* setup the remap window.
|
|
||||||
*/
|
|
||||||
/* Find the bottom of the remap window
|
|
||||||
* is it above 4G?
|
|
||||||
*/
|
|
||||||
remapbasek = 4*1024*1024;
|
|
||||||
if (tomk > remapbasek) {
|
|
||||||
remapbasek = tomk;
|
|
||||||
}
|
|
||||||
/* Find the limit of the remap window */
|
|
||||||
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
|
|
||||||
}
|
|
||||||
/* Write the ram configuration registers,
|
|
||||||
* preserving the reserved bits.
|
|
||||||
*/
|
|
||||||
tolm_r = pci_read_config16(mc_dev, 0xc4);
|
|
||||||
tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
|
|
||||||
pci_write_config16(mc_dev, 0xc4, tolm_r);
|
|
||||||
|
|
||||||
remapbase_r = pci_read_config16(mc_dev, 0xc6);
|
|
||||||
remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
|
|
||||||
pci_write_config16(mc_dev, 0xc6, remapbase_r);
|
|
||||||
|
|
||||||
remaplimit_r = pci_read_config16(mc_dev, 0xc8);
|
|
||||||
remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
|
|
||||||
pci_write_config16(mc_dev, 0xc8, remaplimit_r);
|
|
||||||
|
|
||||||
/* Report the memory regions */
|
|
||||||
idx = 10;
|
|
||||||
ram_resource(dev, idx++, 0, 640);
|
|
||||||
ram_resource(dev, idx++, 768, tolmk - 768);
|
|
||||||
if (tomk > 4*1024*1024) {
|
|
||||||
ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
|
|
||||||
}
|
|
||||||
if (remaplimitk >= remapbasek) {
|
|
||||||
ram_resource(dev, idx++, remapbasek,
|
|
||||||
(remaplimitk + 64*1024) - remapbasek);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
assign_resources(&dev->link[0]);
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
|
||||||
{
|
|
||||||
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
|
|
||||||
return max;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations pci_domain_ops = {
|
|
||||||
.read_resources = pci_domain_read_resources,
|
|
||||||
.set_resources = pci_domain_set_resources,
|
|
||||||
.enable_resources = enable_childrens_resources,
|
|
||||||
.init = 0,
|
|
||||||
.scan_bus = pci_domain_scan_bus,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void cpu_bus_init(device_t dev)
|
|
||||||
{
|
|
||||||
initialize_cpus(&dev->link[0]);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void cpu_bus_noop(device_t dev)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct device_operations cpu_bus_ops = {
|
|
||||||
.read_resources = cpu_bus_noop,
|
|
||||||
.set_resources = cpu_bus_noop,
|
|
||||||
.enable_resources = cpu_bus_noop,
|
|
||||||
.init = cpu_bus_init,
|
|
||||||
.scan_bus = 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void enable_dev(struct device *dev)
|
|
||||||
{
|
|
||||||
/* Set the operations if it is a special bus type */
|
|
||||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
|
||||||
dev->ops = &pci_domain_ops;
|
|
||||||
pci_set_method_conf1();
|
|
||||||
}
|
|
||||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
|
||||||
dev->ops = &cpu_bus_ops;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
struct chip_operations northbridge_intel_e7501_ops = {
|
struct chip_operations northbridge_intel_e7501_ops = {
|
||||||
CHIP_NAME("Intel E7501 northbridge")
|
CHIP_NAME("Intel E7501 northbridge")
|
||||||
.enable_dev = enable_dev,
|
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
|
@ -0,0 +1,2 @@
|
||||||
|
config chip.h
|
||||||
|
object root_complex.o
|
|
@ -0,0 +1,5 @@
|
||||||
|
struct northbridge_intel_e7501_root_complex_config
|
||||||
|
{
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct chip_operations northbridge_intel_e7501_root_complex_ops;
|
|
@ -0,0 +1,193 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <bitops.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
|
||||||
|
|
||||||
|
static void pci_domain_read_resources(device_t dev)
|
||||||
|
{
|
||||||
|
struct resource *resource;
|
||||||
|
unsigned reg;
|
||||||
|
|
||||||
|
/* Initialize the system wide io space constraints */
|
||||||
|
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||||
|
resource->limit = 0xffffUL;
|
||||||
|
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||||
|
|
||||||
|
/* Initialize the system wide memory resources constraints */
|
||||||
|
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||||
|
resource->limit = 0xffffffffULL;
|
||||||
|
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ram_resource(device_t dev, unsigned long index,
|
||||||
|
unsigned long basek, unsigned long sizek)
|
||||||
|
{
|
||||||
|
struct resource *resource;
|
||||||
|
|
||||||
|
if (!sizek) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
resource = new_resource(dev, index);
|
||||||
|
resource->base = ((resource_t)basek) << 10;
|
||||||
|
resource->size = ((resource_t)sizek) << 10;
|
||||||
|
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
|
||||||
|
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void tolm_test(void *gp, struct device *dev, struct resource *new)
|
||||||
|
{
|
||||||
|
struct resource **best_p = gp;
|
||||||
|
struct resource *best;
|
||||||
|
best = *best_p;
|
||||||
|
if (!best || (best->base > new->base)) {
|
||||||
|
best = new;
|
||||||
|
}
|
||||||
|
*best_p = best;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t find_pci_tolm(struct bus *bus)
|
||||||
|
{
|
||||||
|
struct resource *min;
|
||||||
|
uint32_t tolm;
|
||||||
|
min = 0;
|
||||||
|
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
|
||||||
|
tolm = 0xffffffffUL;
|
||||||
|
if (min && tolm > min->base) {
|
||||||
|
tolm = min->base;
|
||||||
|
}
|
||||||
|
return tolm;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pci_domain_set_resources(device_t dev)
|
||||||
|
{
|
||||||
|
struct resource *resource, *last;
|
||||||
|
device_t mc_dev;
|
||||||
|
uint32_t pci_tolm;
|
||||||
|
|
||||||
|
pci_tolm = find_pci_tolm(&dev->link[0]);
|
||||||
|
mc_dev = dev->link[0].children;
|
||||||
|
if (mc_dev) {
|
||||||
|
/* Figure out which areas are/should be occupied by RAM.
|
||||||
|
* This is all computed in kilobytes and converted to/from
|
||||||
|
* the memory controller right at the edges.
|
||||||
|
* Having different variables in different units is
|
||||||
|
* too confusing to get right. Kilobytes are good up to
|
||||||
|
* 4 Terabytes of RAM...
|
||||||
|
*/
|
||||||
|
uint16_t tolm_r, remapbase_r, remaplimit_r;
|
||||||
|
unsigned long tomk, tolmk;
|
||||||
|
unsigned long remapbasek, remaplimitk;
|
||||||
|
int idx;
|
||||||
|
|
||||||
|
/* Get the value of the highest DRB. This tells the end of
|
||||||
|
* the physical memory. The units are ticks of 64MB
|
||||||
|
* i.e. 1 means 64MB.
|
||||||
|
*/
|
||||||
|
tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
|
||||||
|
/* Compute the top of Low memory */
|
||||||
|
tolmk = pci_tolm >> 10;
|
||||||
|
if (tolmk >= tomk) {
|
||||||
|
/* The PCI hole does not overlap memory
|
||||||
|
* we won't use the remap window.
|
||||||
|
*/
|
||||||
|
tolmk = tomk;
|
||||||
|
remapbasek = 0x3ff << 16;
|
||||||
|
remaplimitk = 0 << 16;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
/* The PCI memory hole overlaps memory
|
||||||
|
* setup the remap window.
|
||||||
|
*/
|
||||||
|
/* Find the bottom of the remap window
|
||||||
|
* is it above 4G?
|
||||||
|
*/
|
||||||
|
remapbasek = 4*1024*1024;
|
||||||
|
if (tomk > remapbasek) {
|
||||||
|
remapbasek = tomk;
|
||||||
|
}
|
||||||
|
/* Find the limit of the remap window */
|
||||||
|
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
|
||||||
|
}
|
||||||
|
/* Write the ram configuration registers,
|
||||||
|
* preserving the reserved bits.
|
||||||
|
*/
|
||||||
|
tolm_r = pci_read_config16(mc_dev, 0xc4);
|
||||||
|
tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
|
||||||
|
pci_write_config16(mc_dev, 0xc4, tolm_r);
|
||||||
|
|
||||||
|
remapbase_r = pci_read_config16(mc_dev, 0xc6);
|
||||||
|
remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
|
||||||
|
pci_write_config16(mc_dev, 0xc6, remapbase_r);
|
||||||
|
|
||||||
|
remaplimit_r = pci_read_config16(mc_dev, 0xc8);
|
||||||
|
remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
|
||||||
|
pci_write_config16(mc_dev, 0xc8, remaplimit_r);
|
||||||
|
|
||||||
|
/* Report the memory regions */
|
||||||
|
idx = 10;
|
||||||
|
ram_resource(dev, idx++, 0, 640);
|
||||||
|
ram_resource(dev, idx++, 768, tolmk - 768);
|
||||||
|
if (tomk > 4*1024*1024) {
|
||||||
|
ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
|
||||||
|
}
|
||||||
|
if (remaplimitk >= remapbasek) {
|
||||||
|
ram_resource(dev, idx++, remapbasek,
|
||||||
|
(remaplimitk + 64*1024) - remapbasek);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
assign_resources(&dev->link[0]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
||||||
|
{
|
||||||
|
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations pci_domain_ops = {
|
||||||
|
.read_resources = pci_domain_read_resources,
|
||||||
|
.set_resources = pci_domain_set_resources,
|
||||||
|
.enable_resources = enable_childrens_resources,
|
||||||
|
.init = 0,
|
||||||
|
.scan_bus = pci_domain_scan_bus,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void cpu_bus_init(device_t dev)
|
||||||
|
{
|
||||||
|
initialize_cpus(&dev->link[0]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void cpu_bus_noop(device_t dev)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations cpu_bus_ops = {
|
||||||
|
.read_resources = cpu_bus_noop,
|
||||||
|
.set_resources = cpu_bus_noop,
|
||||||
|
.enable_resources = cpu_bus_noop,
|
||||||
|
.init = cpu_bus_init,
|
||||||
|
.scan_bus = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enable_dev(struct device *dev)
|
||||||
|
{
|
||||||
|
/* Set the operations if it is a special bus type */
|
||||||
|
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||||
|
dev->ops = &pci_domain_ops;
|
||||||
|
pci_set_method_conf1();
|
||||||
|
}
|
||||||
|
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||||
|
dev->ops = &cpu_bus_ops;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
struct chip_operations northbridge_intel_e7501_root_complex_ops = {
|
||||||
|
CHIP_NAME("Intel E7501 Root Complex")
|
||||||
|
.enable_dev = enable_dev,
|
||||||
|
};
|
Loading…
Reference in New Issue