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re-indent, so files conform to coding guidelines. 

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
This commit is contained in:
Stefan Reinauer 2011-06-04 10:36:21 -07:00 committed by Cristian Măgherușan-Stanciu
parent c21b054acc
commit 44c1d3111b
2 changed files with 113 additions and 114 deletions
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66
src/mainboard/asrock/e350m1/romstage.c
View File

@ -49,30 +49,27 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: allow caching of flash chip code and data
// (there are no cache-as-ram reliability concerns with family 14h)
__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
__writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
__writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
__writemsr(0xc0010062, 0);
// early enable of PrefetchEnSPIFromHost
if (boot_cpu())
{
__outdword (0xcf8, 0x8000a3b8);
__outdword (0xcfc, __indword (0xcfc) | 1 << 24);
if (boot_cpu()) {
__outdword(0xcf8, 0x8000a3b8);
__outdword(0xcfc, __indword(0xcfc) | 1 << 24);
}
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{
volatile u32 *spiBase = (void *) 0xa0000000;
if (boot_cpu()) {
volatile u32 *spiBase = (void *)0xa0000000;
u32 save;
__outdword (0xcf8, 0x8000a3a0);
save = __indword (0xcfc);
__outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
spiBase [0] |= 1 << 18; // fast read enable
__outdword (0xcfc, save); // clear temp base
__outdword(0xcf8, 0x8000a3a0);
save = __indword(0xcfc);
__outdword(0xcfc, (u32) spiBase | 2); // set temp MMIO base
spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14);
spiBase[0] |= 1 << 18; // fast read enable
__outdword(0xcfc, save); // clear temp base
}
if (!cpu_init_detectedx && boot_cpu()) {
@ -92,8 +89,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
/* Halt if there was a built in self test failure */
post_code(0x34);
@ -109,45 +106,48 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x37);
val = agesawrapper_amdinitreset();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
val);
}
post_code(0x38);
printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
post_code(0x39);
val = agesawrapper_amdinitearly ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
val = agesawrapper_amdinitearly();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
post_code(0x40);
val = agesawrapper_amdinitpost ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
val = agesawrapper_amdinitpost();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
post_code(0x41);
val = agesawrapper_amdinitenv ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
val = agesawrapper_amdinitenv();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
/* Initialize i8259 pic */
post_code(0x41);
setup_i8259 ();
setup_i8259();
/* Initialize i8254 timers */
post_code(0x42);
setup_i8254 ();
setup_i8254();
post_code(0x50);
copy_and_run(0);
post_code(0x54); // Should never see this post code.
}

3
src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
View File

@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <arch/romcc_io.h>
@ -47,7 +46,7 @@ static void sb800_enable_rom(void)
* BIT21: Port Enable for Port 0x80
*/
dword = pci_io_read_config32(dev, 0x48);
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */