cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -200,7 +200,6 @@ struct cb_gpios {
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struct cb_gpio gpios[0];
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};
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#define CB_TAG_CHROMEOS_ACPI 0x0015
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#define CB_TAG_VBNV 0x0019
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#define CB_TAG_VBOOT_HANDOFF 0x0020
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#define CB_TAG_DMA 0x0022
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@ -97,8 +97,6 @@ struct sysinfo_t {
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void *vboot_handoff;
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u32 vboot_handoff_size;
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void *chromeos_acpi_addr;
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u32 chromeos_acpi_size;
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#if IS_ENABLED(CONFIG_LP_ARCH_X86)
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int x86_rom_var_mtrr_index;
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@ -106,14 +106,6 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
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info->gpios[i] = gpios->gpios[i];
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}
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static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)
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{
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struct lb_range *chromeos_acpi = (struct lb_range *) ptr;
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info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);
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info->chromeos_acpi_size = chromeos_acpi->range_size;
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}
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static void cb_parse_mac_addresses(unsigned char *ptr,
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struct sysinfo_t *info)
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{
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@ -357,9 +349,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
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case CB_TAG_GPIO:
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cb_parse_gpios(ptr, info);
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break;
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case CB_TAG_CHROMEOS_ACPI:
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cb_parse_chromeos_acpi(ptr, info);
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break;
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case CB_TAG_VBNV:
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cb_parse_vbnv(ptr, info);
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break;
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@ -290,7 +290,6 @@ struct lb_gpios {
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struct lb_gpio gpios[0];
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};
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#define LB_TAG_CHROMEOS_ACPI 0x0015
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#define LB_TAG_VBNV 0x0019
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#define LB_TAB_VBOOT_HANDOFF 0x0020
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#define LB_TAB_DMA 0x0022
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@ -195,19 +195,6 @@ static void lb_gpios(struct lb_header *header)
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}
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}
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static void lb_chromeos_acpi(struct lb_header *header)
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{
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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struct lb_range *chromeos_acpi;
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chromeos_acpi = (struct lb_range *)lb_new_record(header);
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chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
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chromeos_acpi->size = sizeof(*chromeos_acpi);
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acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
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&chromeos_acpi->range_size);
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#endif
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}
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static void lb_vbnv(struct lb_header *header)
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{
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#if IS_ENABLED(CONFIG_PC80_SYSTEM)
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@ -547,9 +534,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
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/* Record our GPIO settings (ChromeOS specific) */
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lb_gpios(head);
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/* pass along the chromeos_acpi_t buffer address */
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lb_chromeos_acpi(head);
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/* pass along VBNV offsets in CMOS */
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lb_vbnv(head);
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@ -55,6 +55,6 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif /* __SOC_STONEYRIDGE_NVS_H__ */
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@ -53,6 +53,6 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif /* _SOC_APOLLOLAKE_NVS_H_ */
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@ -19,9 +19,6 @@
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#include <stdint.h>
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#include <compiler.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define LPSS_NVS_SIO_DMA1 0
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#define LPSS_NVS_I2C1 1
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#define LPSS_NVS_I2C2 2
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@ -102,7 +102,7 @@ typedef struct global_nvs_t {
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/* Baytrail LPSS (0x1000) */
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device_nvs_t dev;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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void acpi_create_gnvs(global_nvs_t *gnvs);
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#ifdef __SMM__
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@ -20,9 +20,6 @@
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#include <stdint.h>
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#include <compiler.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define LPSS_NVS_SIO_DMA1 0
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#define LPSS_NVS_I2C1 1
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#define LPSS_NVS_I2C2 2
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@ -106,7 +106,7 @@ typedef struct global_nvs_t {
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/* LPSS (0x1000) */
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device_nvs_t dev;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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void acpi_create_gnvs(global_nvs_t *gnvs);
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#if ENV_SMM
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@ -19,9 +19,6 @@
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#include <stdint.h>
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#include <compiler.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define SIO_NVS_DMA 0
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#define SIO_NVS_I2C0 1
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#define SIO_NVS_I2C1 2
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@ -94,7 +94,7 @@ typedef struct global_nvs_t {
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/* Device specific (0x1000) */
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device_nvs_t dev;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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void acpi_create_gnvs(global_nvs_t *gnvs);
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#ifdef __SMM__
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@ -46,7 +46,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif
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@ -19,9 +19,6 @@
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#include <stdint.h>
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#include <compiler.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define LPSS_NVS_SIO_DMA1 0
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#define LPSS_NVS_I2C1 1
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#define LPSS_NVS_I2C2 2
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@ -20,9 +20,6 @@
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#include <stdint.h>
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#include <compiler.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define SIO_NVS_I2C0 0
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#define SIO_NVS_I2C1 1
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#define SIO_NVS_I2C2 2
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@ -102,6 +102,6 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif
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@ -154,7 +154,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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@ -150,7 +150,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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@ -150,7 +150,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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@ -152,7 +152,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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@ -128,7 +128,7 @@ typedef struct global_nvs_t {
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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} __packed global_nvs_t;
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check_member(global_nvs_t, chromeos, 0x100);
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check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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@ -41,6 +41,18 @@
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#define ACTIVE_ECFW_RO 0
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#define ACTIVE_ECFW_RW 1
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/*
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* chromeos_acpi_t portion of ACPI GNVS is assumed to live at
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* 0x100 - 0x1000. When defining global_nvs_t, use check_member
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* to ensure that it is properly aligned:
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*
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* check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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*/
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#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
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/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
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#define GNVS_DEVICE_NVS_OFFSET 0x1000
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typedef struct {
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/* ChromeOS specific */
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u32 vbt0; // 00 boot reason
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