cbtable: remove chromeos_acpi from cbtable

Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.

BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725

Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Joel Kitching 2018-08-17 15:38:59 +08:00 committed by Martin Roth
parent 5846d5727a
commit 44cff7a897
23 changed files with 24 additions and 58 deletions

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@ -200,7 +200,6 @@ struct cb_gpios {
struct cb_gpio gpios[0];
};
#define CB_TAG_CHROMEOS_ACPI 0x0015
#define CB_TAG_VBNV 0x0019
#define CB_TAG_VBOOT_HANDOFF 0x0020
#define CB_TAG_DMA 0x0022

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@ -97,8 +97,6 @@ struct sysinfo_t {
void *vboot_handoff;
u32 vboot_handoff_size;
void *chromeos_acpi_addr;
u32 chromeos_acpi_size;
#if IS_ENABLED(CONFIG_LP_ARCH_X86)
int x86_rom_var_mtrr_index;

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@ -106,14 +106,6 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
info->gpios[i] = gpios->gpios[i];
}
static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)
{
struct lb_range *chromeos_acpi = (struct lb_range *) ptr;
info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);
info->chromeos_acpi_size = chromeos_acpi->range_size;
}
static void cb_parse_mac_addresses(unsigned char *ptr,
struct sysinfo_t *info)
{
@ -357,9 +349,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_GPIO:
cb_parse_gpios(ptr, info);
break;
case CB_TAG_CHROMEOS_ACPI:
cb_parse_chromeos_acpi(ptr, info);
break;
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;

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@ -290,7 +290,6 @@ struct lb_gpios {
struct lb_gpio gpios[0];
};
#define LB_TAG_CHROMEOS_ACPI 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022

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@ -195,19 +195,6 @@ static void lb_gpios(struct lb_header *header)
}
}
static void lb_chromeos_acpi(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
struct lb_range *chromeos_acpi;
chromeos_acpi = (struct lb_range *)lb_new_record(header);
chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
chromeos_acpi->size = sizeof(*chromeos_acpi);
acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
&chromeos_acpi->range_size);
#endif
}
static void lb_vbnv(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_PC80_SYSTEM)
@ -547,9 +534,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
/* pass along the chromeos_acpi_t buffer address */
lb_chromeos_acpi(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);

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@ -55,6 +55,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_STONEYRIDGE_NVS_H__ */

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@ -53,6 +53,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */

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@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2

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@ -102,7 +102,7 @@ typedef struct global_nvs_t {
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__

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@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2

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@ -106,7 +106,7 @@ typedef struct global_nvs_t {
/* LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM

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@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
#define SIO_NVS_DMA 0
#define SIO_NVS_I2C0 1
#define SIO_NVS_I2C1 2

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@ -94,7 +94,7 @@ typedef struct global_nvs_t {
/* Device specific (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__

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@ -46,7 +46,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif

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@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2

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@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
/* Offset in Global NVS where this structure lives */
#define DEVICE_NVS_OFFSET 0x1000
#define SIO_NVS_I2C0 0
#define SIO_NVS_I2C1 1
#define SIO_NVS_I2C2 2

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@ -102,6 +102,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif

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@ -154,7 +154,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */

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@ -150,7 +150,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */

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@ -150,7 +150,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */

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@ -152,7 +152,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */

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@ -128,7 +128,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
check_member(global_nvs_t, chromeos, 0x100);
check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */

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@ -41,6 +41,18 @@
#define ACTIVE_ECFW_RO 0
#define ACTIVE_ECFW_RW 1
/*
* chromeos_acpi_t portion of ACPI GNVS is assumed to live at
* 0x100 - 0x1000. When defining global_nvs_t, use check_member
* to ensure that it is properly aligned:
*
* check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
*/
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
#define GNVS_DEVICE_NVS_OFFSET 0x1000
typedef struct {
/* ChromeOS specific */
u32 vbt0; // 00 boot reason