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google/reef: Correct SD card pins config 

SD CLK and CLK_FB needs to be pulled down by 20K.
SD CD_N is active LOW, needs to be pulled up by 20K
SD WP pin is not connected for uSD cards, enable writes
by default by pulling low by 20K.

BUG=chrome-os-partner:54866
BRANCH=None
TEST=Test with uSD cards.

Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://review.coreboot.org/16057
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Chiranjeevi Rapolu 2016-08-03 14:09:33 -07:00 committed by Duncan Laurie
parent d924fac759
commit 44d0ddcc81
1 changed files with 8 additions and 4 deletions
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12
src/mainboard/google/reef/gpio.h
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@ -59,15 +59,19 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */
/* SDCARD */
PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */
/* Pull down clock by 20K */
PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_N */
/* Card detect is active LOW. Pull up by 20K */
PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
PAD_CFG_NF(GPIO_186, NATIVE, DEEP, NF1), /* SDCARD_LVL_WP */
/* CLK feedback, internal signal, needs 20K pull down */
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
/* No h/w write proect for uSD cards, pull down by 20K */
PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */