tegra132: use pre-existing reset API

coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().

For the existing tegra132 boards remove the unnecessary files
from the build.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.

Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2014-08-05 13:30:38 -05:00 committed by Patrick Georgi
parent 5d98f51b25
commit 44e5e4ce73
8 changed files with 25 additions and 41 deletions

View File

@ -31,11 +31,12 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

View File

@ -18,12 +18,11 @@
*/
#include <arch/io.h>
#include <reset.h>
#include <soc/nvidia/tegra132/gpio.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
gpio_output(GPIO(I5), 0);
while(1);
}

View File

@ -31,9 +31,11 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
romstage-y += reset.c
romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c

View File

@ -18,12 +18,11 @@
*/
#include <arch/io.h>
#include <reset.h>
#include <soc/nvidia/tegra132/gpio.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);
gpio_output(GPIO(I5), 0);
while(1);
}

View File

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__ */

View File

@ -8,6 +8,7 @@ config SOC_NVIDIA_TEGRA132
select ARM_LPAE
select DYNAMIC_CBMEM
select BOOTBLOCK_CONSOLE
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select HAVE_UART_MEMORY_MAPPED
select EARLY_CONSOLE

View File

@ -8,6 +8,7 @@ bootblock-y += i2c.c
bootblock-y += dma.c
bootblock-y += monotonic_timer.c
bootblock-y += padconfig.c
bootblock-y += reset.c
bootblock-y += ../tegra/gpio.c
bootblock-y += ../tegra/i2c.c
bootblock-y += ../tegra/pingroup.c
@ -24,6 +25,7 @@ romstage-y += cbmem.c
romstage-y += timer.c
romstage-y += ccplex.c
romstage-y += clock.c
romstage-y += reset.c
romstage-y += spi.c
romstage-y += i2c.c
romstage-y += dma.c
@ -49,6 +51,7 @@ ramstage-y += i2c.c
ramstage-y += dma.c
ramstage-y += monotonic_timer.c
ramstage-y += padconfig.c
ramstage-y += reset.c
ramstage-y += ../tegra/apbmisc.c
ramstage-y += ../tegra/gpio.c
ramstage-y += ../tegra/i2c.c

View File

@ -17,9 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
#include <reset.h>
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__ */
/*
* Promote cpu_reset() to a hard_reset(). A shallower reset can be added,
* if needed, at a later time.
*/
void cpu_reset(void)
{
hard_reset();
}