From 44ef38f70344f44ee53a3883515246172eb75054 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 May 2020 08:52:07 +0300 Subject: [PATCH] arch/x86: Remove NO_FIXED_XIP_ROM_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- Makefile.inc | 5 +++-- src/cpu/amd/agesa/Kconfig | 1 - src/cpu/amd/pi/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/model_2065x/Kconfig | 1 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/socket_FCBGA559/Kconfig | 1 - src/cpu/x86/Kconfig | 10 ---------- src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/common/block/cpu/Kconfig | 1 - 12 files changed, 3 insertions(+), 22 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 7149c4f63f..86335d9a88 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1177,9 +1177,10 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data" ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y) $(CONFIG_CBFS_PREFIX)/romstage-options += --xip -ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y) +# For efficient MTRR utilisation use natural alignment for romstage. +ifeq ($(CONFIG_SETUP_XIP_CACHE),y) $(CONFIG_CBFS_PREFIX)/romstage-options += --pow2page -endif # CONFIG_NO_FIXED_XIP_ROM_SIZE +endif # CONFIG_SETUP_XIP_CACHE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 35e2f93268..3cd387dba7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG - select NO_FIXED_XIP_ROM_SIZE select SSE2 if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index bc1253856f..7bcfa61546 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_PI select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG - select NO_FIXED_XIP_ROM_SIZE select SSE2 if CPU_AMD_PI diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index a82198a878..af94314f95 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a76a95dc6d..9acde42bcd 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP config SMM_TSEG_SIZE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index e31260588e..2f0ebf9f50 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP - select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d3af4ca3cc..e6e904dccc 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS select MMX select SSE select CPU_HAS_L2_ENABLE_MSR - select NO_FIXED_XIP_ROM_SIZE config DCACHE_RAM_BASE hex diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 07dfe45e64..5394cd023d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -60,16 +60,6 @@ config TSC_SYNC_MFENCE to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs. -config NO_FIXED_XIP_ROM_SIZE - bool - default n - help - The XIP_ROM_SIZE Kconfig variable is used globally on x86 - with the assumption that all chipsets utilize this value. - For the chipsets which do not use the variable it can lead - to unnecessary alignment constraints in cbfs for romstage. - Therefore, allow those chipsets a path to not be burdened. - config SETUP_XIP_CACHE bool depends on !NO_XIP_EARLY_STAGES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1fd9c4072c..326dff2467 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a437db2580..40ac213eb5 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,7 +17,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_CLK_PM diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 67f7563a92..f5e490f82c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select NO_FIXED_XIP_ROM_SIZE config PCIEXP_ASPM bool diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 0882dd8827..8cc572d3b2 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -21,7 +21,6 @@ config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config SOC_INTEL_COMMON_BLOCK_CAR bool default n - select NO_FIXED_XIP_ROM_SIZE help This option allows you to select how cache-as-ram (CAR) is set up.