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intel/braswell: Remove duplicate set_max_freq() prototypes 

Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Kyösti Mälkki 2019-11-06 08:56:18 +02:00 committed by Patrick Georgi
parent c7fa911279
commit 44f1af2996
6 changed files with 2 additions and 34 deletions
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2
src/soc/intel/braswell/bootblock/bootblock.c
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@ -20,11 +20,11 @@
#include <console/console.h> #include <console/console.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <soc/bootblock.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/iosf.h> #include <soc/iosf.h>
#include <soc/lpc.h> #include <soc/lpc.h>
#include <soc/msr.h>
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/spi.h> #include <soc/spi.h>

22
src/soc/intel/braswell/include/soc/bootblock.h
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@ -1,22 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_BOOTBLOCK_H_
#define _SOC_BOOTBLOCK_H_
void set_max_freq(void);
#endif /* _SOC_BOOTBLOCK_H_ */

1
src/soc/intel/braswell/include/soc/msr.h
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@ -41,5 +41,6 @@
/* Read BCLK from MSR */ /* Read BCLK from MSR */
unsigned int cpu_bus_freq_khz(void); unsigned int cpu_bus_freq_khz(void);
void set_max_freq(void);
#endif /* _SOC_MSR_H_ */ #endif /* _SOC_MSR_H_ */

1
src/soc/intel/braswell/include/soc/ramstage.h
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@ -98,7 +98,6 @@ enum {
*/ */
void soc_init_pre_device(struct soc_intel_braswell_config *config); void soc_init_pre_device(struct soc_intel_braswell_config *config);
void soc_init_cpus(struct device *dev); void soc_init_cpus(struct device *dev);
void set_max_freq(void);
void southcluster_enable_dev(struct device *dev); void southcluster_enable_dev(struct device *dev);
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
int SocStepping(void); int SocStepping(void);

1
src/soc/intel/braswell/include/soc/romstage.h
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@ -24,7 +24,6 @@
void gfx_init(void); void gfx_init(void);
void punit_init(void); void punit_init(void);
void set_max_freq(void);
/* romstage.c functions */ /* romstage.c functions */
int chipset_prev_sleep_state(struct chipset_power_state *ps); int chipset_prev_sleep_state(struct chipset_power_state *ps);

9
src/soc/intel/braswell/tsc_freq.c
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@ -17,11 +17,6 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <soc/msr.h> #include <soc/msr.h>
#if ENV_RAMSTAGE
#include <soc/ramstage.h>
#else
#include <soc/romstage.h>
#endif
#include <stdint.h> #include <stdint.h>
static const unsigned int cpu_bus_clk_freq_table[] = { static const unsigned int cpu_bus_clk_freq_table[] = {
@ -57,8 +52,6 @@ unsigned long tsc_freq_mhz(void)
return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
} }
#if !ENV_SMM
void set_max_freq(void) void set_max_freq(void)
{ {
msr_t perf_ctl; msr_t perf_ctl;
@ -91,5 +84,3 @@ void set_max_freq(void)
wrmsr(IA32_PERF_CTL, perf_ctl); wrmsr(IA32_PERF_CTL, perf_ctl);
} }
#endif /* ENV_SMM */